System and method for providing an improved common control bus for use in on-line insertion of line replaceable units in wireless and wireline access systems

• US 20020097564A1
• Filed: 04/20/2001
• Published: 07/25/2002
• Est. Priority Date: 01/19/2001
• Status: Active Grant

• Current Assignee: Access Solutions, Ltd. (LOXAM SAS)
• Original Assignee: Raze Technologies, Inc.
• Inventors: Struhsaker, Paul F., Denton, James S., McGee, Gregory L.
• Granted Patent: US 6,925,516 B2
• Time in Patent Office: Days
• US Class Current: 361/736
• CPC Class Codes: H01Q 1/246 specially adapted for base stations
• CPC Class Codes: H04L 1/0005 applied to payload information
• CPC Class Codes: H04L 1/0009 by adapting the channel coding H04L1/1812 takes precedence
• CPC Class Codes: H04L 1/0017 where the mode-switching is based on Quality of Service requirement
• CPC Class Codes: H04L 1/007 Unequal error protection for format H04L1/0078; for codes per se H03M13/35
• CPC Class Codes: H04L 12/10 Current supply arrangements
• CPC Class Codes: H04L 12/403 with centralised control, e.g. polling
• CPC Class Codes: H04L 12/66 Arrangements for connecting between networks having differing types of switching systems, e.g. gateways
• CPC Class Codes: H04L 2001/0098 Unequal error protection
• CPC Class Codes: H04M 2207/206 composed of PSTN and wireless network
• CPC Class Codes: H04M 2242/04 for emergency applications
• CPC Class Codes: H04M 2242/06 Lines and connections with preferential service
• CPC Class Codes: H04M 3/42 Systems providing special services or facilities to subscribers specially adapted for wireless communication networks H04W4/00
• CPC Class Codes: H04W 28/18 Negotiating wireless communication parameters
• CPC Class Codes: H04W 84/14 WLL [Wireless Local Loop]; RLL [Radio Local Loop]
• CPC Class Codes: H04W 88/021 adapted for Wireless Local Loop operation
• CPC Class Codes: H04W 88/08 Access point devices

Abstract

There is disclosed a system and method for providing an improved common control bus for use in the on-line insertion of line replaceable units (such as circuit board cards) into a backplane of a processor shelf, a modem shelf, or a similar type of equipment. The present invention increases the number of device locations that a common control bus can access. The present invention comprises a complex programmable logic device on a circuit board card that is coupled to a common control bus. The complex programmable logic device is capable of selectively coupling to the common control bus each one of a plurality of device locations on the circuit board card. The complex programmable logic device controls data access to and from each device that is coupled to the common control bus.

Claims

1. For use in association with a backplane of an item of electronic equipment wherein said backplane comprises a common control bus that can access a first number of device locations, an apparatus capable of allowing said common control bus to access more than said first number of device locations, said apparatus comprising:

a complex programmable logic device on a circuit board card within said backplane, wherein said complex programmable logic device is coupled to said common control bus, and wherein said complex programmable logic device is capable of coupling each one of a plurality of device locations on said circuit board card to said common control bus.

2. The system as set forth in claim 1 wherein said complex programmable logic device controls the access of a device to said common control bus when a device location of said device is coupled to said common control bus.

3. The system as set forth in claim 1 wherein said complex programmable logic device couples device locations on said circuit board card to said common control bus to allow said common control bus to access a second number of device locations on said circuit board card through said complex programmable logic device.

4. The system as set forth in claim 3 wherein said second number of device locations on said circuit board card that said common control bus can access through said complex programmable logic device is greater than said first number of device locations that said common control bus can otherwise access.

5. The apparatus as set forth in claim 1 further comprising:

a card processor on said circuit board card within said backplane, said card processor coupled to said common control bus.

6. The apparatus as set forth in claim 5 wherein said card processor is coupled to said common control bus through a serial clock line connection and through a serial data line connection.

7. The apparatus as set forth in claim 5 further comprising:

an electrically erasable programmable read only memory on said circuit board card, said electrically erasable programmable read only memory coupled to said common control bus;

wherein said complex programmable logic device controls the access of said electrically erasable programmable read only memory to said common control bus when said electrically erasable programmable read only memory is coupled to said common control bus.

8. The apparatus as set forth in claim 7 wherein said electrically erasable programmable read only memory is coupled to said common control bus through a serial clock line connection and through a serial data line connection.

9. The apparatus as set forth in claim 7 wherein said complex programmable logic device is coupled to said common control bus through a serial clock line connection and through a serial data line connection.

10. The apparatus as set forth in claim 1 wherein said common control bus comprises a first two wire bus and a second two wire bus, and wherein said apparatus comprises:

a card processor on said circuit board card within said backplane, said card processor coupled to said first two wire bus and to said second two wire bus of said common control bus through metal oxide semiconductor field effect transistor switches;

an electrically erasable programmable read only memory on said circuit board card, said electrically erasable programmable read only memory coupled to said first two wire bus and to said second two wire bus of said common control bus through metal oxide semiconductor field effect transistor switches; and

wherein said complex programmable logic device is coupled to said first two wire bus and to said second two wire bus of said common control bus through metal oxide semiconductor field effect transistor switches.

11. The apparatus as set forth in claim 10 wherein said complex programmable logic device controls the access of said electrically erasable programmable read only memory to said first two wire bus and to said second two wire bus of said common control bus.

13. The method as claimed in claim 12 further comprising the step of:

coupling a second number of device locations on said circuit board card to said common control bus through a complex programmable logic device on said circuit board card.

14. The method as set forth in claim 13 wherein said second number of device locations is greater than said first number of device locations that said common control bus can access not using said complex programmable logic device.

15. The method as claimed in claim 12 further comprising the steps of:

coupling a card processor on said circuit board card within said backplane to said common control bus;

providing clock signals to said card processor from a serial clock line coupled to said common data bus;

reading data from said card processor on a serial data line coupled to said common data bus; and

writing data to said card processor from said serial data line.

16. The method as set forth in claim 12 further comprising the steps of:

coupling a electrically erasable programmable read only memory on said circuit board card within said backplane to said common control bus;

providing clock signals to said electrically erasable programmable read only memory from a serial clock line coupled to said common data bus;

reading data from said electrically erasable programmable read only memory on a serial data line coupled to said common data bus; and

writing data to said electrically erasable programmable read only memory from said serial data line.

17. The method as set forth in claim 16 further comprising the step of:

controlling the access of said electrically erasable programmable read only memory to said common control bus with said complex programmable logic device.

19. The method as set forth in claim 18 further comprising the steps of:

interpreting in said complex programmable logic device a first portion of a first byte of said data to identify a card address for said first device;

interpreting in said complex programmable logic device a second portion of said first byte of said data to identify a device code of said first device; and

interpreting in said complex programmable logic device a third portion of said first byte of said data to identify an instruction to read data or write data to said first device.

20. The method as set forth in claim 19 wherein said first device is one of:

an electrically erasable programmable read only memory, a card processor, a card status register, and a card control register.

12. For use in association with a backplane of an item of electronic equipment wherein said backplane comprises a common control bus that can access a first number of device locations, a method for allowing said common control bus to access more than said first number of device locations, said method comprising the steps of:

coupling each one of a plurality of device locations on said circuit board card to said common control bus through a complex programmable logic device on said circuit board card; and

controlling the access of a device on said circuit board card to said common control bus when a device location of said device is coupled to said common control bus.

18. For use in association with a backplane of an item of electronic equipment wherein said backplane comprises a common control bus that can access a first number of device locations, a method for allowing said common control bus to access more than said first number of device locations, said method comprising the steps of:

coupling a first device on a circuit board card within said backplane to said common control bus;

coupling a complex programmable logic device on said circuit board card to said common control bus and to said first device;

receiving data in said complex programmable logic device through a serial data line coupled to said common data bus; and

interpreting instructions in said data to allow said complex programmable logic device to control data access to said first device.