Micro-electromechanical process for fabrication of integrated multi-frequency communication passive components

• US 20020098611A1
• Filed: 11/07/2001
• Published: 07/25/2002
• Est. Priority Date: 11/18/2000
• Status: Active Grant

• Current Assignee: Lenghways Technology Company Limited
• Original Assignee: Lenghways Technology Company Limited
• Inventors: Huang, Jung-Tang, Chang, Pei-Zen, Lin, Hung-Hsuan
• Granted Patent: US 6,607,934 B2
• Time in Patent Office: Days
• US Class Current: 438/50
• CPC Class Codes: B81C 1/00246 Monolithic integration, i.e. micromechanical structure and electronic processing unit are integrated on the same substrate
• CPC Class Codes: B81C 2203/0735 Post-CMOS, i.e. forming the micromechanical structure after the CMOS circuit
• CPC Class Codes: H01H 59/0009 making use of micromechanics
• CPC Class Codes: H01L 2924/16153 Cap enclosing a plurality of side-by-side cavities [e.g. E-shaped cap]
• CPC Class Codes: H03H 7/0115 comprising only inductors and capacitors H03H7/075, H03H7/09, H03H7/12, H03H7/13 take precedence

Abstract

A micro-electromechanical (MEM) process for fabrication of integrated multi-frequency communication passive components is fused into co-fired ceramics by way of “flip chip” for fabrication of a low-cost, high-performance, and high-reliability hybrid communication passive component applicable in the frequency range of 0.9 GHz˜100 GHz. The basic structure of the passive component is a double-layer substrate comprising a low-loss ceramic or glass bottom-layer substrate and a glass or plastic poly-molecular top-layer substrate and an optional ceramic substrate at the lowest layer. As the materials used and the processing temperature in the MEM process is compatible with the CMOS process, thus this invention is fit for serving as a post process following the CMOS process.

Claims

1. A micro-electromechanical (MEM) process for fabrication of integrated multi-frequency communication passive components, wherein the MEM process is fused into co-fired ceramics to produce a hybrid communication component;

the passive components are built on a multi-layer substrate, wherein a bottom-layer substrate is a low-loss substrate such as ceramic or glass substrate while a top-layer is a polymer or glass substrate; and

the materials employed and temperature conditions in the MEM process are fully compatible with the CMOS process, the MEM process is therefore fit for serving as a post process of the latter.

2. The micro-electromechanical (MEM) process according to claim 1, wherein the fabrication process of the bottom-layer substrate comprises:

sputtering to form a layer of metallic compound (TaNx) on the substrate to serve as a thin-film resistor layer, patterning with lithography, then performing wet- or dry-etching process as step #1;

sputtering or electroless-plating to form a seeding layer on the substrate as step #2;

spin coating a polyimide layer as a molding plate for electroplating as step #3;

vapor-depositing to form an aluminum layer to serve for an etching mask as step #4;

patterning with lithography and removing the undesired portion of the aluminum layer by wet-etching as step #5;

performing reacting ion etching (RIE) O₂, or O₂+CHF₃ to remove the polyimide layer as step #6;

removing the upmost aluminum layer as step #7;

forming a copper layer on the seeding layer by direct electroplating, then planarizing the copper layer by chemical mechanical polishing (CMP) to form a metallic bottom layer of inductance and a bottom electrode of capacitance and switches as step #8;

forming a layer of high dielectric constant at a proper position by sputtering method or chemical vapor deposition (CVD) to serve for a dielectric layer of capacitance as step #9;

forming an top seeding layer on the substrate by sputtering or electroless-plating approach as step #10;

forming a polyimide layer as done in steps #3˜

#7 as step #11;

forming a metallic layer (Ni) as a second metallic layer serving for a sacrifice layer as step #12;

forming a polyimide layer as done in steps #3˜

#7 as step #13;

depositing a copper layer on the second metallic layer to serve for a base of inductance, meanwhile, a top electrode of capacitance and switches as step #14;

forming a ceramic layer (such as a silicon dioxide layer) to serve for a mechanical structure of microswitch as step #15;

forming a polyimide layer as done in steps #3˜

#7 as step #16;

depositing a copper layer to serve for a top metallic layer of inductance as step #17;

etching the polyimide layer by the plasma etching method as step #18;

removing nickel to have a cantilever of the top electrode of switches suspended as step #19;

removing the second seeding layer by wet-etching process as step #20;

etching to remove the remaining polyimide layer by the plasma etching method as step #21; and

removing the first seeding layer by wet-etching process to have the bottom-layer substrate structured completely as step #22.

3. The micro-electromechanical (MEM) process according to claim 1, wherein the top-layer substrate is made of low-cost plexiglass or polymer material.

4. The micro-electromechanical (MEM) process according to claim 1, wherein the MEM process is integrated with low-temperature co-fired ceramics by perforating a plurality of via holes in the bottom-layer substrate and forming a plurality of bumps on back thereof so that the bumps are connected with the upmost-layer circuit of an LTCC package and a soldering pad to form a “

flip chip”

package.

5. The micro-electromechanical (MEM) process according to claim 3, wherein the top-layer substrate is a polymer structure and the cover thereof is provided with via holes and cavities to become fit for hot-embossing operation;

the required precise molds are prepared following the steps (A) through (H);

Poly Methyl Methacrylate (PMMA) is hot-embossed or mold-injected with nickel molds according to step (I);

the desired circuitry is electroplated as per steps (J) through (N); and

all the steps are described briefly as the following;

(A) Growing a silicon-oxide film in thickness of 5000 Å

on a silicon wafer;

(B) Spin coating photoresist, then, masking and developing;

(C) Etching the silicon wafer with SF₆/O₂ plasma, the first time plasma etching, to form a via hole;

(D) Removing the photoresist with O₂ plasma;

(E) Etching the silicon wafer with SF₆/O₂ plasma, the second time plasma etching;

(F) Coating insulation lacquer on the bottom surface of a silicon substrate and electroless-plating a seeding layer on the front surface of the silicon substrate, and electroplating the substrate with nickel;

(G) Chemical mechanical polishing to planarize the nickel layer;

(H) Removing silicon base to obtain a nickel mold;

(I) Hot-embossing the PMMA layer with the nickel mold;

(J) Electroless-plating a seeding layer on the pressed PMMA layer;

(K) Coating an electrical deposition photoresist to perform a standard lithography process;

(L) Electroplating copper;

(M) Removing the photoresist and flash-etching the seeding layer; and

(N) Having a required cover comprising a patch antenna, a via hole, and two isolation cavities.

6. The micro-electromechanical (MEM) process according to claim 3, wherein the fabrication process of a glass-made top-layer substrate comprises:

plating the via holes of the substrate and depositing to emerge the shape of antenna;

using a Ti/Au mask to define an etching window in the case of a shallow etching depth limited in some-ten micrometers, then etching the substrate with KOH agent to form an annular undercut;

or etching with a sand blaster to form an annular undercut of the substrate in the case of a etching depth in some-ten micrometers up; and

depositing a metallic layer on the bottom surface of the substrate, namely, the other end of the antenna, for shielding.

7. The micro-electromechanical (MEM) process according to claim 1, wherein the mentioned “

materials employed and temperature conditions in the MEM process are fully compatible with the CMOS process”

is supplemented here in other words after reviewing all the processing conditions, such as temperature, materials, etc., in claim 2, as;

“

irrespective of an alumina substrate, even a circuit-laid silicon wafer processed by way of the CMOS process can be further treated with the process of this invention without any impairment to the existing CMOS circuit, therefore, this invention is fit for serving as a post process following the CMOS process.”

8. A micro-electromechanical (MEM) process for fabrication of integrated multi-frequency communication passive components, which is applicable to different frequency bands, wherein components in different specifications or requirements are separated, then fabricated by a micro-electromechanical (MEM) process, which is fused into co-fired ceramics, to form an integrated hybrid communication passive component on a multi-layer substrate comprising a low-loss ceramic or glass bottom-layer substrate and a polymer or glass top-layer substrate with isolation design between components and transmission lines to meet requirements of small area and high integrating density.

9. The micro-electromechanical (MEM) process according to claim 8, wherein the mentioned “

different frequency bands”

is made by slicing the working frequency into a plurality of bands;

some passive components, particularly filters and antennas, can be aligned in different combinations in a “

distributed”

or “

lumped”

or a hybrid manner while signal is transmitted by the structure of coplanar waveguide (CPW) or microstrip lines;

the inductance is known changed in different frequencies, and for maintaining high Q of this invention, a solenoid inductor is adopted, in which a ferromagnetic core or a low dielectric-coefficient core is inserted respectively for high-frequency or low-frequency applications.

10. The micro-electromechanical (MEM) process according to claim 8, wherein the mentioned “

isolation design between components and transmission lines”

is to use a metallic shield for besetting by forming two rows of via holes in a LTCC package to be fenced by connecting microstrip lines to confine the electromagnetic waves thereof.

11. The micro-electromechanical (MEM) process according to claim 8, wherein the isolation design is realized by etching a top cover to form cavities in a corresponding shape with the microstrip lines, in which the cavities are metal-plated and grounded, or etching out a part of the substrate under the microstrip lines to beset the electromagnetic waves of the microstrip lines.

12. The micro-electromechanical (MEM) process according to claim 8, wherein the isolation design is realized by introducing a high dielectric-constant material for channeling.

13. The micro-electromechanical (MEM) process according to claim 8, wherein the fusion of MEM process into co-fired ceramics is performed for fabrication of some low-accuracy components for cost-saving.

14. The micro-electromechanical (MEM) process according to claim 8, wherein the frequency band is divided into a low-frequency band at 0.9 GHz˜

5 GHz;

a middle-frequency band at 5 GHz˜

30 GHz; and

a high-frequency band at 30 GHz up.