Multilevel copper interconnects with low-k dielectrics and air gaps
First Claim
1. A multilevel wiring interconnect in an integrated circuit, comprising:
- a number of multilayer metal lines connecting to a number of silicon devices in a substrate;
a low dielectric constant insulator in a number of interstices between the number of multilayer metal lines and the substrate; and
wherein the low dielectric constant insulator includes a number of air gaps in the low dielectric constant material.
1 Assignment
0 Petitions
Accused Products
Abstract
Structures and methods are provided for an improved multilevel wiring interconnect in an integrated circuit assembly. The present invention provides for a multilayer copper wiring structure by electroless, selectively deposited copper in a streamlined process which further reduces both intra-level line to line capacitance and the inter-level capacitance.
In particular, an illustrative embodiment of the present invention includes a novel methodology for forming multilevel wiring interconnects in an integrated circuit assembly. The method includes forming a number of multilayer metal lines, e.g. copper lines formed by selective electroless plating, separated by air gaps above a substrate. A low dielectric constant material is deposited between the number of metal lines and the substrate using a directional process. According to the teachings of the present invention, using a directional process includes maintaining a number of air gaps in the low dielectric constant material. Structures and systems are similarly included in the present invention.
117 Citations
20 Claims
-
1. A multilevel wiring interconnect in an integrated circuit, comprising:
-
a number of multilayer metal lines connecting to a number of silicon devices in a substrate;
a low dielectric constant insulator in a number of interstices between the number of multilayer metal lines and the substrate; and
wherein the low dielectric constant insulator includes a number of air gaps in the low dielectric constant material. - View Dependent Claims (2, 3, 4, 5, 6)
-
-
7. An integrated circuit, comprising:
-
at least one semiconductor device formed in a substrate;
a number of multilayer metal lines connecting to a number of silicon devices in a substrate;
a low dielectric constant insulator in a number of interstices between the number of multilayer metal lines and the substrate; and
wherein the low dielectric constant insulator includes a number of air gaps in the low dielectric constant material. - View Dependent Claims (8, 9, 10, 11, 12, 14, 15, 16, 18, 19, 20)
-
-
13. An integrated circuit, comprising:
-
a substrate including one or more transistors;
a number of multilayer Copper lines connecting to one or more of the transistors in the substrate;
a low dielectric constant insulator in a number of interstices between the number of multilayer Copper lines and the substrate; and
wherein the low dielectric constant insulator includes a number of air gaps in the low dielectric constant material.
-
-
17. A system, comprising:
-
a processor; and
an integrated memory circuit coupled to the processor, wherein the integrated memory circuit further includes a multilevel wiring interconnect, the multilevel wiring interconnect comprising;
a number of multilayer Copper lines connecting to one or more of the transistors in the substrate;
a low dielectric constant insulator in a number of interstices between the number of multilayer Copper lines and the substrate; and
wherein the low dielectric constant insulator includes a number of air gaps in the low dielectric constant material.
-
Specification