Processor

• US 20020099924A1
• Filed: 01/24/2002
• Published: 07/25/2002
• Est. Priority Date: 03/17/1995
• Status: Active Grant

• Current Assignee: Renesas Electronics Corporation
• Original Assignee: Hitachi, Ltd.
• Inventors: Tanaka, Kazuhiko, Kojima, Keiji, Kurokawa, Yoshiki, Nojiri, Toru, Nishioka, Kiyokazu, Fujikawa, Yoshifumi, Terada, Koichi, Hosoki, Koji
• Granted Patent: US 6,965,981 B2
• Time in Patent Office: Days
• US Class Current: 712/24
• CPC Class Codes: G06F 9/30036 Instructions to perform operations on packed data, e.g. vector, tile or matrix operations
• CPC Class Codes: G06F 9/30112 comprising data of variable length
• CPC Class Codes: G06F 9/30167 of immediate specifier, e.g. constants
• CPC Class Codes: G06F 9/30178 of compressed or encrypted instructions
• CPC Class Codes: G06F 9/30181 Instruction operation extension or modification
• CPC Class Codes: G06F 9/30189 according to execution mode, e.g. mode flag
• CPC Class Codes: G06F 9/32 Address formation of the next instruction, e.g. by incrementing the instruction counter G06F9/38 takes precedence
• CPC Class Codes: G06F 9/38 Concurrent instruction execution, e.g. pipeline or look ahead
• CPC Class Codes: G06F 9/3802 Instruction prefetching
• CPC Class Codes: G06F 9/3816 Instruction alignment, e.g. cache line crossing
• CPC Class Codes: G06F 9/3822 Parallel decoding, e.g. parallel decode units
• CPC Class Codes: G06F 9/3836 Instruction issuing, e.g. dynamic instruction scheduling or out of order instruction execution
• CPC Class Codes: G06F 9/3853 of compound instructions
• CPC Class Codes: G06F 9/3854 Instruction completion, e.g. retiring, committing or graduating
• CPC Class Codes: G06F 9/3885 using a plurality of independent parallel functional units
• CPC Class Codes: G06F 9/3887 controlled by a single instruction for multiple data lanes [SIMD]
• CPC Class Codes: G06F 9/3891 organised in groups of units sharing resources, e.g. clusters

Abstract

An object of the prevent invention is to provide a processor that can execute many computations with a small number of instruction codes.

As far as multimedia processing is concerned, a plurality of computations of a same type are often executed concurrently and hence a plurality of computing units having a same function are used and mode information for controlling the plurality of units by an instruction unit for one computing unit is prepared in each instruction to execute a plurality of computations with a single instruction.

Claims

1. A processor, comprising:

a memory for storing an instruction code and data;

an instruction code holding means for a plurality of instruction codes read from said memory; and

a plurality of computing units operating in parallel according to the plurality of instruction codes held in said instruction code holding means;

wherein each computing unit includes a plurality of computing devices and a plurality of access port register files, each of said plurality of computing devices reading a content of each of said register files from a corresponding access port for computation, and said plurality of computing units each having a same function.

3. A processor according to claim 1, wherein at least one computing device in said computing unit can execute a data transfer instruction for transferring data between said memory and said register file.

2. A processor comprising:

a memory for storing an instruction code and data;

an instruction code holding means for holding a plurality of instruction codes read from said memory; and

a plurality of computing units operating in parallel according to the plurality of instruction codes held in said instruction code holding means;

wherein each computing unit includes a plurality of computing devices and a plurality of access port register files, each of said plurality of computing devices reading from a corresponding access port for computation, and said plurality of computing units each has a subset of devices having a same function.

4. A processor according to claim 2, wherein at least one computing device in said computing unit can execute a data transfer for transferring data between said memory and said register file.