Method and apparatus for waking up a circuit and applications thereof

• US 20020099966A1
• Filed: 01/25/2001
• Published: 07/25/2002
• Est. Priority Date: 01/25/2001
• Status: Abandoned Application

• Current Assignee: SigmaTel Incorporated (NXP Semiconductors NV)
• Original Assignee: SigmaTel Incorporated (NXP Semiconductors NV)
• Inventors: Cabler, Carlin D.
• Application Number:
  US09/769,543
• Publication Number:
  US 20020099966A1
• Time in Patent Office: Days
• US Class Current: 713/323
• CPC Class Codes: G06F 1/3209 Monitoring remote activity, e.g. over telephone lines or network connections
• CPC Class Codes: H04L 12/12 Arrangements for remote connection or disconnection of substations or of equipment thereof
• CPC Class Codes: H04M 11/06 Simultaneous speech and data transmission, e.g. telegraphic transmission over the same conductors
• CPC Class Codes: Y02D 30/50 in wire-line communication networks, e.g. low power modes or reduced link rate

Abstract

A method and apparatus for waking up a circuit includes processing that begins by determining whether a signal is present on a data path by a 1^st detection module. The 1^st detection module is designed with passive components such that it consumes a minimal amount of power. In addition, the 1^st detection module detects the presence of any signal on the received path using the energy of the signal. When a signal is detected, a 2^nd detection module is enabled to determine whether a characteristic of the signal is one of a known set of characteristics. The known set of characteristics includes a phase relationship, magnitude, power level, frequency, and/or any other characteristic a telecommunication system may have. When the characteristic of the signal is one of the known set of characteristics, the digital circuitry of a modem is enabled.

Claims

1. A wake up circuit comprises:

first detection module operably coupled to a data path to determine whether a signal is present on the data path, wherein, when the signal is detected on the data path, the first detection module produces an enable signal; and

second detection module operable based on the enable signal, wherein, when the enable signal is produced, the second detection module is operably coupled to determine whether a characteristic of the signal is one of a known set of characteristics, wherein, when the characteristic is one of the known set of characteristics, the second detection module provides a signal present signal, and wherein the second detection module is inoperable when the enable signal is not produced.

2. The wake up circuit of claim 1 further comprises:

a third detection module operable based on the signal present signal, wherein, when the signal present signal is produced, the third detection module is operably coupled to determine whether the signal is a particular type of signal, wherein, when the signal is the particular type of signal, the third detection module produces a system wake-up signal, and wherein the third detection module is inoperable when the signal present signal is not produced.

3. The wake up circuit of claim 2, wherein the third detection module further comprises:

first memory for storing a digital representation of the signal;

second memory for storing at least one start-up sequence of a data transmission protocol; and

comparator operably coupled to compare the digital representation of the signal with the at least one start-up sequence of a data transmission protocol, wherein, when the signal substantially matches one of the at least one start-up sequence of a data transmission protocol, the comparator generates the system wake-up signal.

4. The wake up circuit of claim 1, wherein the first detection module comprises:

diode having an anode and a cathode, wherein the anode is operably coupled to receive the signal;

capacitor having a first plate and a second plate, wherein, the first plate is coupled to the cathode and the second plate is coupled to a reference potential;

first resistor coupled in parallel with the capacitor;

transistor having a gate, drain, and source, wherein the gate is coupled to the cathode and the source is coupled to the reference potential;

inverter having an input and an output, wherein the input is coupled to the drain and the output provides the enable signal; and

second resistor operably coupled to the input of the inverter and to a source potential.

5. The wake up circuit of claim 1, wherein the second detection module comprises:

filter operably coupled to filter the signal to produce a filtered signal;

rectifier operably coupled to rectify the filtered signal to produce a rectified signal; and

level detection module operably coupled to determine whether at least one of energy level and magnitude of the rectified signal exceeds a characteristic threshold, such that when the at least one of the energy and the magnitude exceeds the characteristic threshold, the characteristic is one of the known set of characteristics.

6. The wake up circuit of claim 5, wherein the data path comprises at least one of:

base band wireless communication path;

pass band wireless communication path;

base band wire line communication path; and

pass band wire line communication path.

7. The wake up circuit of claim 6, wherein the filter further comprises:

band pass filter when the data path is the pass band wireless communication path or the pass band wire line communication path; and

low pass filter when the data path is the base band wireless communication path or the base band wire line communication path.

8. An analog front end comprises:

transmit path that includes;

digital to analog converter operably coupled to convert a digital transmit signal into an analog transmit signal;

line driver operably coupled to amplify energy of the analog transmit signal to produce an amplified analog transmit signal;

receive path that includes;

filter having an input and an output, wherein the input is operably coupled to receive an analog receive signal, wherein the filter filters and amplifies the analog receive signal to produce a filtered analog receive signal;

oversampling quantizer operably coupled to convert the filtered analog receive signal into a stream of digital data;

decimation filter operably coupled to decimate the stream of digital data into a digital receive signal;

wake up circuit operably coupled to disable the digital portions of the transmit and receive paths until a viable analog receive signal is detected, the wake up circuit includes;

first detection module operably coupled to determine whether a signal is present at the input of the filter, wherein, when the signal is detected at the input of the filter, the first detection module produces an enable signal; and

second detection module operable based on the enable signal, wherein, when the enable signal is produced, the second detection module is operably coupled to determine whether a characteristic of the signal is one of a known set of characteristics of the analog receive signal, wherein, when the characteristic is one of the known set of characteristics, the second detection module provides a signal present signal, and wherein at least some of the digital portions of the transmit and receive paths are enabled based on the signal present signal.

9. The analog front end of claim 8 further comprises:

digital signal processor that processes the digital receive signal and the digital transmit signal based on a data transmission protocol, wherein the digital signal processor is disabled until activation of a system wake-up signal; and

a third detection module operable based on the signal present signal, wherein, when the signal present signal is produced, the third detection module is operably coupled to determine whether the digital receive signal is a particular type of signal, wherein, when the digital receive signal is the particular type of signal, the third detection module produces a system wake-up signal, and wherein the third detection module is inoperable when the signal present signal is not produced.

10. The analog front end of claim 9 further comprises the second detection module is operably coupled to the analog to digital converter and the decimation filter, wherein, when the signal present signal is generated, the analog to digital converter and the decimation filter are enabled.

11. The analog front end of claim 9, wherein the third detection module further comprises:

first memory for storing a digital representation of the signal;

second memory for storing at least one start-up sequence of a data transmission protocol; and

comparator operably coupled to compare the digital representation of the signal with the at least one start-up sequence of a data transmission protocol, wherein, when the signal substantially matches one of the at least one start-up sequence of a data transmission protocol, the comparator generates the system wake-up signal.

12. The analog front end of claim 8, wherein the first detection module comprises:

diode having an anode and a cathode, wherein the anode is operably coupled to receive the signal;

capacitor having a first plate and a second plate, wherein, the first plate is coupled to the cathode and the second plate is coupled to a reference potential;

first resistor coupled in parallel with the capacitor;

transistor having a gate, drain, and source, wherein the gate is coupled to the cathode and the source is coupled to the reference potential;

inverter having an input and an output, wherein the input is coupled to the drain and the output provides the enable signal; and

second resistor operably coupled to the input of the inverter and to a source potential.

13. The analog front end of claim 8, wherein the second detection module comprises:

filter operably coupled to filter the signal to produce a filtered signal;

rectifier operably coupled to rectify the filtered signal to produce a rectified signal; and

level detection module operably coupled to determine whether at least one of energy level and magnitude of the rectified signal exceeds a characteristic threshold, such that when the at least one of the energy and the magnitude exceeds the characteristic threshold, the characteristic is one of the known set of characteristics.

15. The method of claim 14, wherein the determining whether the signal is of the particular type of signal further comprises:

storing a digital representation of the signal;

comparing the digital representation of the signal with at least one start-up sequence of a data transmission protocol; and

when the signal substantially matches one of the at least one start-up sequence of a data transmission protocol, generating the system wake-up signal.

16. The method of claim 14, wherein the determining whether a signal is present on a data path further comprises:

integrating the signal to produce an integrated signal; and

comparing the integrated signal with a signal threshold;

when the integrated signal compares favorably with the signal threshold, indicating that the signal is present.

17. The method of claim 14, wherein the determining whether a characteristic of the signal is one of a known set of characteristics further comprises:

filtering the signal to produce a filtered signal;

rectifying the filtered signal to produce a rectified signal;

determining whether at least one of energy level and magnitude of the rectified signal exceeds a characteristic threshold; and

when the at least one of the energy and the magnitude exceeds the characteristic threshold, determining that the characteristic is one of the known set of characteristics.

19. The apparatus of claim 18, wherein the memory further comprises operational instructions that cause the processing module to determine whether the signal is of the particular type of signal by:

storing a digital representation of the signal;

comparing the digital representation of the signal with at least one start-up sequence of a data transmission protocol; and

when the signal substantially matches one of the at least one start-up sequence of a data transmission protocol, generating the system wake-up signal.

20. The apparatus of claim 18, wherein the memory further comprises operational instructions that cause the processing module to determine whether a signal is present on a data path by:

integrating the signal to produce an integrated signal; and

comparing the integrated signal with a signal threshold;

when the integrated signal compares favorably with the signal threshold, indicating that the signal is present.

21. The apparatus of claim 18, wherein the memory further comprises operational instructions that cause the processing module to determine whether a characteristic of the signal is one of a known set of characteristics by:

filtering the signal to produce a filtered signal;

rectifying the filtered signal to produce a rectified signal;

determining whether at least one of energy level and magnitude of the rectified signal exceeds a characteristic threshold; and

when the at least one of the energy and the magnitude exceeds the characteristic threshold, determining that the characteristic is one of the known set of characteristics.

14. A method for waking up a circuit, the method comprises the steps of:

determining whether a signal is present on a data path;

when the signal is detected on the data path, determining whether a characteristic of the signal is one of a known set of characteristics;

when the characteristic is one of the known set of characteristics, determining whether the signal is a particular type of signal; and

when the signal is the particular type of signal, producing a system wake-up signal.

18. An apparatus for waking up a circuit, the apparatus comprises:

processing module; and

memory operably coupled to the processing module, wherein the memory stores operational instructions that cause the processing module to;

determine whether a signal is present on a data path;

when the signal is detected on the data path, determine whether a characteristic of the signal is one of a known set of characteristics;

when the characteristic is one of the known set of characteristics, determine whether the signal is a particular type of signal; and

when the signal is the particular type of signal, produce a system wake-up signal.