Method and system for selecting a master controller in a redundant control plane having plural controlllers

• US 20020099972A1
• Filed: 11/15/2001
• Published: 07/25/2002
• Est. Priority Date: 01/25/2001
• Status: Active Grant

• Current Assignee: Ericsson AB (Telefonaktiebolaget LM Ericsson)
• Original Assignee: Crescent Networks, Inc.
• Inventors: Walsh, Robert J., Barbas, Steve N., Friend, James F.
• Granted Patent: US 6,886,107 B2
• Time in Patent Office: Days
• US Class Current: 714/10
• CPC Class Codes: G06F 11/2005 using redundant communication controllers
• CPC Class Codes: G06F 11/2007 using redundant communication media
• CPC Class Codes: G06F 11/2028 eliminating a faulty processor or activating a spare
• CPC Class Codes: G06F 11/2038 with a single idle spare processing component

Abstract

A system and method for configuring a control plane within a network device. One of a pair of control processors is selected to act as the master of the control plane and the other control processor is specified as a standby control processor in normal operation. In the case of a failover or switchover event, the standby control processor assumes the role of the master of the control plane and updates configuration information within line cards in the network device as necessary. A state machine within the control processor is employed to manage state transitions for the control processor. Each control processor generates at least one signal that indicates whether it is capable of serving as the master of the control plane. Master selection logic selects one of the control processors as the master for the control plane and in one embodiment advertises the identification of the master control processor via triply redundant signals. Voting logic within the control processors and other cards within the network device is employed to identify the selected master unit for the control plane. The selected master control plane processor forwards the configuration information over control paths that are isolated from the data path within the network device.

Claims

1. Apparatus for configuring a control plane in a network device having at least one line card for receiving and transmitting data, said at least one line card being communicably coupled to at least one switch fabric via at least one data path, said apparatus comprising:

first and second control plane processor elements, each operative to generate at least one status signal indicative of the operational status of the respective processor element;

first and second control paths associated with said first and second control plane processor elements respectively and communicably coupling said first and second control plane processor elements respectively to said at least one line card, said first and second control paths being isolated from said at least one data path;

selection logic operative in response to said at least one status signal from said first and second control plane processor elements for generating at least one identification signal for identifying one of said first and second control plane processor elements as an Master control plane processor and for communicating said at least one identification signal to said first and second control plane processor elements;

one of said first and second control plane processor elements being operative in response to receipt of said at least one identification signal to configure itself as said active control plane processor element; and

said active control plane processor element being operative to transmit configuration information over the associated control path to said at least one line card.

2. The apparatus of claim 1 wherein said configuration information includes at least one forwarding table.

3. The apparatus of claim 1 wherein said configuration information includes at least one software image for execution on said at least one line card.

4. The apparatus of claim 1 wherein said at least one identification signal comprises a triply redundant identification signal and each one of said first and second control plane processor elements includes voting logic for identifying said first processor element as said active control plane processor element if at least two of said triply redundant identification signals are of a first state and for identifying said second processor element as said active control plane processor element as said active control plane processor element if at least two of said triply redundant identification signals are of a second state.

5. The apparatus of claim 1 further including interface logic communicably coupling said first and second control plane processor elements, said active control plane processor element being operative to transmit state information regarding said active control plane processor element to said standby control plane processor element via said interface logic.

6. The apparatus of claim 1 further including first and second interface logic, each of said first and second interface logic communicably coupling said first and second control plane processor elements, said first and second interface logic being responsive to said at least one identification signal to identify one of said first and second interface logic as active interface logic and the other one of said first and second interface logic as standby interface logic, said active control plane processor element being operative to transmit state information regarding said active control plane processor element to said standby control plane processor element via said active interface logic.

7. The apparatus of claim 1 wherein said at least one status signal includes first and second status signals, said first signal indicating in a first state that the respective control plane processor element has passed a first predetermined set of diagnostics and is capable of acting as said active control plane processor element, said second signal comprising a timeout signal that assumes a timeout state if the respective control plane processor element does not pass a second predetermined set of diagnostics that are run generally periodically.

8. The apparatus of claim 7 wherein said active control plane processor element ceases to function as said active control plane element and the other control plane processor element is configured as said active control plane processor element in the event (i) said second signal within said active control plane processor element assumes said timeout state, (ii) said first signal of said other control plane processor element is in said first state, and (iii) said second signal of said other control plane processor element has not assumed said timeout state.

9. The apparatus of claim 8 wherein said second predetermined set of diagnostics are executed approximately ten times per second.

10. A method for configuring a control plane in a network device, wherein said network device includes at least one line card for receiving and transmitting data over corresponding communication links, said at least one line card being communicably coupled to at least one switch fabric via at least one data path, wherein said at least one line card, said at least one data path and said at least one switch fabric comprise a data plane, said method comprising the steps of:

generating at least one status signal at first and second control plane processor elements, each of said at least one signal being indicative of the ability of the respective control plane processor element to function as an active control plane processor element for said control plane;

communicating said at least one status signal from said first and second control plane processor elements to selection logic;

generating within said selection logic at least one identification signal responsive to at least one status signal from said first and second control plane processor elements, said identification signal for identifying one of said first and second control plane processor element as said active control plane processor element;

communicating said at least one identification signal from said selection logic to said first and second control plane processor elements;

responsive to receipt of said at least one identification signal at said first and second control plane processor elements, configuring one of said first and second control plane processor elements as an active control plane processor element and the other one of said processor elements as a standby control plane processor element; and

transmitting first configuration information from said active control plane processor element to said at least one line card over a first control path isolated from said at least one data path.

11. The method of claim 10 further including the step of communicating state information regarding said active control plane processor element to said standby control plane processor element.

12. The method of claim 11 wherein the third communicating step includes communicating state information regarding said active control plane processor element to said standby control plane processor element via an interface electrically coupling said active and standby control plane processor elements.

13. The method of claim 10 wherein said at least one identification signal comprises a triply redundant identification signal and said method includes the step of verifying that at least two of said triply redundant identification signals are of a first state to identify said first control plane processor element as said active control plane processor element and that two of said three triply redundant identification signals are of a second state to identify said second control plane processor element as said active control plane processor element.

14. The method of claim 10 wherein said step of generating at least one status signal comprises the step of generating first and second signals;

said step of generating said first signal comprises the step of executing a first predetermined set of diagnostics in each control plane processor element that tests the ability of the respective control plane processor element to act as said active control plane processor element and generating said first signal in a first state if the respective control plane processor element has passed said first predetermined set of diagnostics, and

said step of generating said second signal comprises the step of executing a second predetermined set of diagnostics within each of said control plane processor elements and producing said second signal in a timeout state if the respective control plane processor element does not pass said second predetermined set of diagnostics.

15. The method of claim 14 wherein said step of executing said second predetermined set of diagnostics comprises the step of executing said second predetermined set of diagnostics generally periodically.

16. The method of claim 15 wherein said step of executing said second predetermined set of diagnostics includes the step of determining whether the respective control plane processor element can establish communications with a network device controller.

17. The method of claim 15 wherein said step of executing said second predetermined set of diagnostics includes the step of determining whether any runtime errors have been detected by the respective control plane processor element within the respective period.

18. The method of claim 15 wherein said step of executing said second predetermined set of diagnostics includes the step of executing said first predetermined set of diagnostics.

19. The method of claim 14 further including the step of reconfiguring said standby control plane processor element as a new active control plane processor element and reconfiguring said active control plane processor element as an inactive control plane processor element in the event (i) said second signal within said active control plane processor element assumes said timeout state, (ii) said first signal of said standby control plane processor element is in said first state, and (iii) said second signal of said standby control plane processor element has not assumed said timeout state.

20. The method of claim 19 wherein said steps of reconfiguring said active and standby control plane processor elements includes the step of generating a new at least one identification signal that identifies said standby control plane processor element as said new active control plane processor element and performing said reconfiguring steps in response to receipt of said new at least one new identification signal at said first and second control plane processor elements.

21. The method of claim 20 further including the step of communicating state information regarding said new active control plane processor element to said inactive control plane processor element following said reconfiguring steps.

22. The method of claim 10 further including the step of generating by said selection logic said at least one identification signal in a predetermined state to select a predetermined one of said first and second control plane processor elements as said active control plane processor elements if said at least one status signal from said first and second control plane processor elements indicate that both control plane processor elements are functional.