System for reducing test data volume in the testing of logic products
First Claim
1. A method for reducing test data volume in the testing of logic product under test, comprising the steps of:
- (a) generating original test vector data including care bits and non-care bits;
(b) filling said non-care bits with a repeated value to form a highly compressible test vector data set;
(c) compressing said highly compressible test vector data set to form a compressed test vector data set;
(d) simulating the product under test with test input data to determine the expected responses generated from the product under test in response to the test input data; and
(e) compressing the expected test response data into a compact error-detecting expected signature.
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Accused Products
Abstract
A system for reducing test data volume in the testing of logic products such as modules on integrated circuit chips, and systems comprised of multiple integrated circuit chips. Test stimulus data are loaded from a tester into the logic product to apply to portions of combinational logic circuitry therein in order to detect faults comprises “care” bits and “non-care” bits. The care bits target focal faults of interest in the logic circuitry being tested while the non-care bits do not. Non-care bits in the test vector data are filled with repetitive, repeating, or other background data sequences. The background data sequences are constructed such that they can be algorithmically recovered from a small amount of initialization data. The recovery can use hardware that is located in the product under test, inside the tester, or between the product under test and the tester, or software residing in the tester and operating while the test is performed. The software and/or hardware recover the full test input stimulus data including the fill data from the much more compact source data. The use of a compacted data format for the fill data provides for a high degree of compressibility of the total test input stimulus vector data set. The method for test data reduction combines the compact data representation for the input stimulus data with on-product or off-product compression of the test response data. The response data compression can be accomplished by the use of error-detecting codes, by comparing the responses from several identical products under test. The combination of data compression techniques for both, test input stimulus data and test output response data, results in significantly better overall data reduction.
48 Citations
18 Claims
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1. A method for reducing test data volume in the testing of logic product under test, comprising the steps of:
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(a) generating original test vector data including care bits and non-care bits;
(b) filling said non-care bits with a repeated value to form a highly compressible test vector data set;
(c) compressing said highly compressible test vector data set to form a compressed test vector data set;
(d) simulating the product under test with test input data to determine the expected responses generated from the product under test in response to the test input data; and
(e) compressing the expected test response data into a compact error-detecting expected signature. - View Dependent Claims (2, 3, 4, 5, 6, 7, 8, 9, 10, 11, 12, 13, 14, 15, 16, 17, 18)
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Specification