Field effect transistor having a lateral depletion structure

• US 20020100933A1
• Filed: 01/30/2001
• Published: 08/01/2002
• Est. Priority Date: 01/30/2001
• Status: Active Grant

• Current Assignee: Semiconductor Components Industries LLC (ON Semiconductor Corporation)
• Original Assignee: Fairchild Semiconductor Corporation (ON Semiconductor Corporation)
• Inventors: Marchant, Bruce D.
• Granted Patent: US 6,713,813 B2
• Time in Patent Office: Days
• US Class Current: 257/330
• CPC Class Codes: H01L 29/0634 Multiple reduced surface field (multi-RESURF) structures, e.g. double RESURF, charge compensation, cool, superjunction (SJ), 3D-RESURF, composite buffer (CB) structures
• CPC Class Codes: H01L 29/1095 Body region, i.e. base region, of DMOS transistors or IGBTs cell layout H01L29/0696
• CPC Class Codes: H01L 29/7813 with trench gate electrode, e.g. UMOS transistors trench gate electrodes per se H01L29/4236

Abstract

A field effect transistor device and a method for making a field effect transistor device are disclosed. The field effect transistor device includes a stripe trench extending from the major surface of a semiconductor substrate into the semiconductor substrate to a predetermined depth. The stripe trench contains a semiconductor material of the second conductivity type to form a PN junction at an interface formed with the semiconductor substrate.

Claims

1. A field effect transistor device comprising:

a semiconductor substrate of a first conductivity type having a major surface and a drain region;

a well region of a second conductivity type formed in the semiconductor substrate;

a source region of the first conductivity type formed in the well region;

a trench gate electrode formed adjacent to the source region; and

a stripe trench extending from the major surface of the semiconductor substrate into the semiconductor substrate to a predetermined depth, the stripe trench containing a semiconductor material of the second conductivity type to form a PN junction at an interface formed with the semiconductor substrate.

2. The field effect transistor device of claim 1 wherein the first conductivity type comprises N type and the second conductivity type comprises P type.

3. The field effect transistor device of claim 1 wherein the gate electrode comprises polysilicon.

4. The field effect transistor device of claim 1 wherein the stripe trench extends from the major surface to the drain region.

5. The field effect transistor device of claim 1 wherein the device is a power MOSFET which has a breakdown voltage between about 100 and about 400 volts.

6. The field effect transistor device of claim 1 wherein the stripe trench further contains a dielectric material lining the stripe trench and wherein the semiconductor material of the second conductivity type is disposed in the lining.

7. The field effect transistor device of claim 1 wherein the semiconductor substrate includes an epitaxial portion.

8. The field effect transistor device of claim 7 wherein the epitaxial portion has a thickness less than about 40 microns.

9. The field effect transistor device of claim 7 wherein the epitaxial portion includes a drift region.

10. The field effect transistor device of claim 7 wherein the epitaxial portion has a resistivity less than 14 ohm-cm.

11. The field effect transistor device of claim 1 wherein the drain region comprises an N+ semiconductor material.

13. The method of claim 12 wherein forming a stripe trench occurs after forming a source region.

14. The method of claim 12 wherein the first conductivity type comprises N type and the second conductivity type comprises P type.

15. The method of claim 12 wherein the semiconductor substrate has an orientation and wherein the stripe trench is perpendicular to the orientation of the semiconductor substrate.

16. The method of claim 12 wherein the gate electrode comprises polysilicon.

17. The method of claim 12 wherein the semiconductor material of the second type comprises epitaxial silicon.

18. The method of claim 12 wherein forming the stripe trench occurs after the gate structure, the well region and the source region are formed.

19. The method of claim 12 wherein the method further comprises

depositing a dielectric material in the stripe trench.

26. The field effect transistor device of claim 1 wherein the stripe trench extends through the well region.

12. A method of forming a field effect transistor device comprising:

forming a well region of a second conductivity type in a semiconductor substrate of a first conductivity type, the semiconductor substrate having a major surface and a drain region;

forming a source region of the first conductivity type in the well region;

forming a trench gate electrode adjacent to the source region;

forming a stripe trench extending from the major surface of the semiconductor substrate into the semiconductor substrate to a predetermined depth; and

depositing a semiconductor material of the second conductivity type within the stripe trench.

20. A method of forming a field effect transistor device comprising:

a) forming a well region of a second conductivity type in a semiconductor substrate of a first conductivity type having a major surface and a drain region;

b) forming a source region of the first conductivity type formed in the well region;

c) forming a gate electrode adjacent to the source region;

d) forming a stripe trench extending from the major surface of the semiconductor substrate into the semiconductor substrate to a predetermined depth; and

e) depositing a semiconductor material of the second conductivity type within the stripe trench,

wherein at least one of steps a), b), and c) occurs after step e).

21. The method of claim 20 wherein steps d) and e) are performed after steps a), b), and c).

22. The method of claim 20 wherein the gate electrode is a trench gate electrode.

23. The method of claim 20 wherein first conductivity type comprises N type and the second conductivity type comprises P type.

24. The method of claim 20 wherein forming the stripe trench comprises anisotropic etching.

25. A field effect transistor device made according to the process of claim 20.