High voltage semiconductor device

• US 20020100934A1
• Filed: 01/31/2002
• Published: 08/01/2002
• Est. Priority Date: 01/31/2001
• Status: Active Grant

• Current Assignee: North Plate Semiconductor, LLC
• Original Assignee: Kabushiki Kaisha Toshiba (Toshiba Corporation)
• Inventors: Matsudai, Tomoko, Nakagawa, Akio
• Granted Patent: US 6,617,641 B2
• Time in Patent Office: Days
• US Class Current: 257/330
• CPC Class Codes: H01L 29/0834 Anode regions of thyristors or gated bipolar-mode devices, e.g. supplementary regions surrounding anode regions
• CPC Class Codes: H01L 29/36 characterised by the concentration or distribution of impurities in the bulk material within semiconductor regions H01L29/06
• CPC Class Codes: H01L 29/7397 and a gate structure lying on a slanted or vertical surface or formed in a groove, e.g. trench gate IGBT

Abstract

An IGBT has a punch-through structure including an n⁺ buffer layer. It includes a p⁻ low concentration layer formed between the n⁺ buffer layer and a p⁺ drain layer. Owing to the low concentration layer, the drain current decreases to zero gradually, not rapidly, when the IGBT is turned off.

Claims

1. A semiconductor device comprising:

a drain layer of a first conductivity type;

a buffer layer of a second conductivity type formed above the drain layer;

a high resistance layer of the second conductivity type formed on the buffer layer;

a base layer of the first conductivity type formed on the high resistance layer;

a source layer of the second conductivity type, containing a high concentration of impurities, formed in a surface region of the base layer;

a gate electrode formed in the base layer with an insulating film interposed therebetween; and

a low concentration layer formed between the drain layer and the buffer layer, an impurity concentration of the low concentration layer being lower than those of the drain layer and the buffer layer.

2. The device according to claim 1, wherein a total amount of impurities contained in the drain layer is at most 5×

10¹⁴ cm<sup>−

2</sup>.

3. The device according to claim 1, wherein the low concentration layer is of first or second conductivity type.

4. The device according to claim 3, wherein a portion of the low concentration layer, which has a concentration at most ½

of a maximum concentration of the buffer layer, is at least 0.5 μ

m and at most 30 μ

m thick.

5. The device according to claim 3, wherein a portion of the low concentration layer, which has a concentration at most ½

of a maximum concentration of the buffer layer, is at least 1 μ

m and at most 20 μ

m thick.

6. The device according to claim 3, wherein the impurity concentration of the low concentration layer is lower than ⅕

of that of the buffer layer.

7. The device according to claim 3, wherein the impurity concentration of the low concentration layer is at most 1×

10¹⁶ cm<sup>−

3</sup>.

8. The device according to claim 3, wherein a total amount or impurities contained in the low concentration layer is less than {fraction (1/10)} of that of the buffer layer.

9. The device according to claim 1, further comprising a region, whose lifetime is short, provided between the low concentration layer and the buffer layer.

10. The device according to claim 1, further comprising a region, whose lifetime is short, provided inside the low concentration layer.

11. The device according to claim 1, wherein the gate electrode is a trench gate.

12. The device according to claim 1, wherein the gate electrode is a planar gate.

14. The device according to claim 13, wherein a total amount of impurities contained in the drain layer is at most 5×

10¹⁴ cm<sup>−

2</sup>.

15. The device according to claim 13, wherein the low concentration layer is of first or second conductivity type.

16. The device according to claim 15, wherein a portion of the low concentration layer, which has a concentration at most ½

of a maximum concentration of the buffer layer, is at least 0.5 μ

m and at most 30 μ

m thick.

17. The device according to claim 15, wherein a portion of the low concentration layer, which has a concentration at most ½

of a maximum concentration of the buffer layer, is at least 1 μ

m and at most 20 μ

m thick.

18. The device according to claim 15, wherein the impurity concentration of the low concentration layer is lower than ⅕

of that of the buffer layer.

19. The device according to claim 15, wherein the impurity concentration of the low concentration layer is at most 1×

10¹⁶ cm<sup>−

3</sup>.

20. The device according to claim 15, wherein a total amount of impurities contained in the low concentration layer is less than {fraction (1/10)} of that of the buffer layer.

21. The device according to claim 13, further comprising a region, whose lifetime is short, provided inside the low concentration layer.

22. The device according to claim 13, wherein the gate electrode is a trench gate.

23. The device according to claim 13, wherein the gate electrode is a planar gate.

13. A semiconductor device comprising:

a drain layer of a first conductivity type;

a buffer layer of a second conductivity type formed above the drain layer;

a high resistance layer of the second conductivity type formed on the buffer layer;

a base layer of the first conductivity type formed on the high resistance layer;

a source layer of the second conductivity type, containing a high concentration of impurities, formed in a surface region of the base layer;

a gate electrode formed in the base layer with an insulating film interposed therebetween; and

a drain electrode to supply a potential to the drain layer,

the drain layer having high concentration layers, whose impurity concentration is high, on sides near the buffer layer and the drain electrode, and a low concentration layer, whose impurity concentration is low, between the high concentration layers.