Method of manufacturing semiconductor device, and semiconductor device manufactured thereby

• US 20020100943A1
• Filed: 06/26/2001
• Published: 08/01/2002
• Est. Priority Date: 01/31/2001
• Status: Abandoned Application

• Current Assignee: Mitsubishi Denki Kabushiki Kaisha (Mitsubishi Electric Corporation)
• Original Assignee: Mitsubishi Denki Kabushiki Kaisha (Mitsubishi Electric Corporation)
• Inventors: Sogo, Yasunori, Ogata, Tamotsu
• Application Number:
  US09/888,386
• Publication Number:
  US 20020100943A1
• Time in Patent Office: Days
• US Class Current: 257/382
• CPC Class Codes: H01L 21/28518 the conductive layers comprising silicides H01L21/28537 takes precedence
• CPC Class Codes: H01L 21/76828 thermal treatment
• CPC Class Codes: H01L 21/76832 Multiple layers
• CPC Class Codes: H01L 21/76834 formation of thin insulating films on the sidewalls or on top of conductors H01L21/76831 takes precedence
• CPC Class Codes: H01L 21/823418 with a particular manufacturing method of the source or drain structures, e.g. specific source or drain implants or silicided source or drain structures or raised source or drain structures
• CPC Class Codes: H10B 12/05 Making the transistor
• CPC Class Codes: H10B 12/09 with simultaneous manufacture of the peripheral circuit region and memory cells

Abstract

In the process of manufacturing a semiconductor device that has a silicide layer, a buffer film is interposed between the silicide layer and the insulating film to protect the silicide layer from direct influence of the stress imposed by the insulating film. For instance, in a logic circuit region of a semiconductor device, a silicide layer is formed on an impurity region. Then, the silicide layer is covered by a buffer layer, and the buffer layer is covered by an interlayer insulating film. The buffer layer is so formed as to alleviate stress imposed on the silicide layer by the interlayer insulating film.

Claims

1. A method of manufacturing a semiconductor device, comprising the steps of:

forming a silicide layer on the surface of an impurity region formed on a semiconductor substrate;

forming a buffer film which directly covers the silicide layer; and

forming an insulating film on the buffer film, the buffer film alleviating stress imposed on the silicide layer by the insulating film.

2. The method of manufacturing a semiconductor device according to claim 1, further comprising the steps of:

forming an interlayer insulating film on the insulating film; and

forming a contact hole which penetrates through the interlayer insulating film, the insulating film, and the buffer film and reaches the silicide layer.

3. The method of manufacturing a semiconductor device according to claim 1, wherein an oxide film is formed as the buffer film without oxidizing the silicide layer.

4. The method of manufacturing a semiconductor device according to claim 3, wherein the oxide film is formed through use of a CVD system having a load lock mechanism, without involvement of oxidation of the silicide layer.

5. The method of manufacturing a semiconductor device according to claim 3, wherein the oxide film is formed by setting a temperature, at which the semiconductor substrate is to be introduced into a CVD reactor, at 400°

C. or less, without involvement of oxidation of the silicide layer.

6. A method of manufacturing a semiconductor device including a memory region and a logic circuit region on a semiconductor substrate, the method comprising the steps of:

forming a silicide layer on the surface of an impurity region within the logic circuit region;

forming a buffer film, which directly covers the silicide layer, in the logic circuit region having the silicide layer formed thereon and in the memory region;

forming a resist pattern on top of at least the silicide layer within the logic circuit region, and removing the buffer film from the memory region by means of etching with the resist pattern used as a mask; and

forming an insulating film so as to cover the logic circuit region and the memory region, wherein the buffer film alleviates stress imposed by the insulating film on the silicide layer located within the logic circuit region.

7. The method of manufacturing a semiconductor device according to claim 6, further comprising the steps of:

forming an interlayer insulating film on the insulating film; and

forming a contact hole which penetrates through the interlayer insulating film, the insulating film, and the buffer film and reaches the silicide layer.

8. A semiconductor device comprising:

a semiconductor substrate;

a gate insulating film formed on the semiconductor substrate;

a gate electrode formed on the gate insulating film;

an impurity region formed on the surface of the semiconductor substrate adjacent to the gate electrode,

a silicide layer formed on the surface of the impurity regions adjacent to the gate electrode; and

a buffer film formed to directly cover the silicide layer;

an insulating film formed on the buffer film, the buffer film alleviating the stress imposed by the insulating film on the silicide layer.