INTEGRATED CMOS ACTIVE PIXEL DIGITAL CAMERA

• US 20020101528A1
• Filed: 01/22/1998
• Published: 08/01/2002
• Est. Priority Date: 01/22/1998
• Status: Active Grant

• Current Assignee: Omnivision Technologies Incorporated (Will Semiconductor Co., Ltd. Shanghai)
• Original Assignee: Eastman Kodak Company
• Inventors: GUIDASH, ROBERT M., LEE, PAUL P., BERNSTEIN, LAWRENCE J., LEE, TEH-HSUANG
• Granted Patent: US 6,721,008 B2
• Time in Patent Office: Days
• US Class Current: 348/304
• CPC Class Codes: H04N 25/76 Addressed sensors, e.g. MOS or CMOS sensors

Abstract

An image sensor device comprising a silicon substrate having a plurality of CMOS circuit formed thereon, including a pixel array having a plurality of rows and a plurality of columns, a row addressing circuit operatively connected to each the pixel array and the timing control circuit, the row addressing circuit having a row bus that provides address lines to each row in the pixel array, a column addressing circuit, a pixel timing circuit, a timing control logic block, a signal processing circuit, and an interface circuit coupled to external computational means for provision of address and control signals to the sensor device, the interface circuit being operatively coupled the timing control logic, the pixel timing circuit, the row addressing circuit and the column addressing circuit.

Claims

1. An image sensor device comprising:

a silicon substrate having a plurality of CMOS circuit formed thereon;

a pixel array having a plurality of rows and a plurality of columns formed within the substrate;

a timing control logic block formed within the substrate;

a row addressing circuit formed within the substrate and operatively connected to each the pixel array and the timing control circuit, the row addressing circuit having a row bus that provides address lines to each row in the pixel array;

a column addressing circuit formed within the substrate;

a pixel timing circuit formed within the substrate;

a signal processing circuit contained within the substrate; and

an interface circuit coupled to external computational means for provision of commands used by the sensor to generate address and control signals to the sensor device, the interface circuit being operatively coupled the timing control logic, the pixel timing circuit, the row addressing circuit and the column addressing circuit.

2. The invention of claim 1 wherein the timing control logic block further comprises an electronic shuttering control circuit.

3. The invention of claim 2 wherein the electronic shuttering control circuit further comprises a circuit that is programmable responsive to an input from the interface circuit.

4. The invention of claim 3 wherein the electronic shuttering control circuit is responsive to electronic shuttering mode data received from the interface circuit relating to one of the following:

adjustment of electronic shuttering mode;

clearing pixels relative to frame time;

integration time for each frame;

or fluorescent light beating.

5. The image sensor device of claim 1 further comprising a signal processing circuit coupled to the pixel array to receive data output from the array.

6. The image sensor device of claim 5 wherein the signal processing circuit further comprises a correlated double sampling circuit.

7. The image sensor device of claim 5 wherein the signal processing circuit further comprises a noise reduction circuit.

8. The image sensor device of claim 7 wherein the noise reduction circuit further comprises a fixed pattern noise removal circuit.

9. The image sensor device of claim 5 wherein the signal processing circuit is further comprises an analog to digital converter.

10. An semiconductor image sensing device comprising:

an imaging array containing a plurality of pixels formed on a semiconductor substrate;

a timing control block formed on the substrate programmable via a serial communications interface formed on the substrate;

means for generating signal required to address and readout the pixel values formed on the substrate;

means form processing the pixel values to form digital words formed on the substrate; and

means for delivering the digital words to external devices.

11. The device of claim 10 further comprising means for selecting a predetermined set of pixels from the imaging array contained within the timing control block.

12. The device of claim 10 further comprising means for performing electronic shuttering contained within the timing control block.

13. The device of claim 10 further comprising means for selecting a subset of pixels for exposure determination within the timing control block.

14. The device of claim 10 further comprising means for power conservation contained within the timing control block.

15. The device of claim 10 wherein the timing control block further comprises means for providing a signal which is delivered external to the device for synchronizing with a mechanical shutter.

16. The device of claim 10 wherein the timing control block further comprises means for providing a signal which is delivered external to the device for synchronizing with a strobe light.

17. The device of claim 10 further comprising a Microcontroller embedded within the sensor device, the Microcontroller further comprising interface means for user input.

18. The device of claim 17 further comprising an ASIC designed for interfacing the Microcontroller to the remaining portions of the sensor device.

19. The device of claim 10 further comprising an embedded memory associated with the ADC output.

20. The device of claim 19 wherein the embedded memory further comprises a data buffering mechanism which allows different speeds of reads and writes to the mechanism.