Non-volatile semiconductor memory device having sensitive sense amplifier structure

• US 20020101775A1
• Filed: 08/20/2001
• Published: 08/01/2002
• Est. Priority Date: 01/31/2001
• Status: Active Grant

• Current Assignee: Renesas Electronics Corporation
• Original Assignee: Mitsubishi Denki Kabushiki Kaisha (Mitsubishi Electric Corporation)
• Inventors: Nojiri, Isao, Ohba, Atsushi, Kai, Yoshihide
• Granted Patent: US 6,611,468 B2
• Time in Patent Office: Days
• US Class Current: 365/207
• CPC Class Codes: G11C 11/5642 Sensing or reading circuits; Data output circuits
• CPC Class Codes: G11C 16/28 using differential sensing or reference cells, e.g. dummy cells

Abstract

In a non-volatile semiconductor memory device, a constant current circuit is arranged in parallel with an NMOS diode converting a detected current on the array cell side to a voltage, and a constant current circuit is arranged in parallel with an NMOS diode converting a detected current on the reference cell side to a voltage. Constant current circuits supply an offset current. Thus, a difference between two input voltages of a differential amplifier increases.

Claims

1. A non-volatile semiconductor memory device, comprising:

a non-volatile memory cell;

a reference cell for determining storage data of said memory cell;

a differential amplifier detecting a difference between voltages at first and second input nodes;

a first current voltage converting element connected to said first input node for converting a first read current from said memory cell to a voltage;

a second current voltage converting element connected to said second input node for converting a second read current from said reference cell to a voltage; and

a gain adjusting circuit adjusting a detection sensitivity of said differential amplifier by adjusting values of said first and second read currents.

2. The non-volatile semiconductor memory device according to claim 1, wherein said first and second current voltage converting elements respectively include diode elements, and said gain adjusting circuit includes a constant current circuit for supplying offset currents to said first and second input nodes.

3. The non-volatile semiconductor memory device according to claim 2, wherein said constant current circuit includes a first current circuit connected to said first input node, and a second constant current circuit connected to said second input node.

4. The non-volatile semiconductor memory device according to claim 3, wherein said first and second constant current circuits supply substantially same currents.

5. The non-volatile semiconductor memory device according to claim 1, wherein said gain adjusting circuit includes

a drive circuit generating a current having a value lower than that of said second read current based on said second read current for converting said generated current to a voltage,

a first element connected to said first input node for supplying a first offset current based on the voltage obtained from said drive circuit, and

a second element connected to said second input node for supplying a second offset current based on the voltage obtained from said drive circuit.

6. The non-volatile semiconductor memory device according to claim 5, wherein said first and second offset currents have substantially same current values.

7. The non-volatile semiconductor memory device according to claim 1, wherein said gain adjusting circuit includes

a drive circuit generating a current having a value lower than said second read current based on said second read current for converting said generated current to a voltage,

first element connected to said first input node for supplying a current having a value lower than that of said second read current to said second current voltage converting element, and

a second element connected to said second input node for supplying an offset current based on the voltage obtained from said drive circuit.

8. The non-volatile semiconductor memory device according to claim 1, wherein said first and second current voltage converting elements respectively include resistive elements, and said gain adjusting circuit includes a constant current circuit for supplying offset currents to said first and second input nodes.

9. A non-volatile semiconductor memory device, comprising:

a non-volatile memory cell capable of operating in n (said n is an integer of at least

     3) storage states;

k (said k is an integer of at least

     2) reference cells for determining said n storage states;

k first current voltage converting elements each converting a first read current of said memory cell to a voltage;

k second current voltage converting element converting said k second read currents from said k reference cells to voltages;

k differential amplifiers detecting differences between an output from said first current voltage converting element and respective outputs from said k second current voltage converting elements; and

a gain adjusting circuit adjusting each detection sensitivity of said k differential amplifiers by adjusting values of said k second read currents and said first read current.

10. The non-volatile semiconductor memory device according to claim 9, wherein said first current voltage converting elements and said k second current voltage converting elements respectively include diode elements, and said gain adjusting circuit includes a constant current circuit for reducing input currents to said first current voltage converting element and at least one of said k second current voltage converting elements.

11. The non-volatile semiconductor memory device according to claim 9, wherein said gain adjusting circuit includes a constant current circuit varying input currents to said first current voltage converting element and said k second current voltage converting elements according to detection sensitivities of said k differential amplifiers.

12. The non-volatile semiconductor memory device according to claim 11, wherein said constant current circuit provides substantially same input currents to said k second current voltage converting elements.

13. The non-volatile semiconductor memory device according to claim 11, wherein said constant current circuit includes a circuit generating (k−

j) offset currents using j (where j is an integer of at least 1 and at most (k−

1)) of said k second read currents, and said (k−

j) offset currents reduce input currents to (k−

j) said second current voltage converting elements.

14. The non-volatile semiconductor memory device according to claim 9, wherein said first current voltage converting element and said k second current voltage converting elements respectively include resistive elements, and said gain adjusting circuit includes a constant current circuit for reducing input currents to said first current voltage converting element and at least one of said k second current voltage converting elements.