Field coupled power MOSFET bus architecture using trench technology

• US 20020102795A1
• Filed: 03/25/2002
• Published: 08/01/2002
• Est. Priority Date: 01/27/1998
• Status: Active Grant

• Current Assignee: Semiconductor Components Industries LLC (ON Semiconductor Corporation)
• Original Assignee: Fairchild Semiconductor Corporation (ON Semiconductor Corporation)
• Inventors: Calafut, Daniel S.
• Granted Patent: US 6,673,680 B2
• Time in Patent Office: Days
• US Class Current: 438/259
• CPC Class Codes: H01L 29/4236 within a trench, e.g. trench gate electrode, groove gate electrode
• CPC Class Codes: H01L 29/7813 with trench gate electrode, e.g. UMOS transistors trench gate electrodes per se H01L29/4236

Abstract

A power metal oxide semiconductor-field-effect-transistor (MOSFET) device using trench technology to achieve a reduced-mask-production process. The power MOSFET device includes a gate signal bus having multiple gate trenches formed using fewer masks than previously required for a similar device. The two-dimensional behavior of the trenches provides an advantageous field-coupling effect that suppresses hot-carrier generation without the need for the commonly used thick layer of silicon dioxide beneath the gate polysilicon. The use of easily controlled silicon trench etching in production of the power MOSFET results in stable, low cost, and high yielding manufacturing.

Claims

1. A process for fabricating a power device comprising the steps of:

etching multiple gate bus trenches into a top surface of a region of a substrate wherein said region surrounding the trenches comprises a dopant carriers of only one type polarity with a concentration selected to the deplete dopant carriers from portions of the region bordering the trenches at chosen operating voltages in order for merging together the depletion regions beneath a gate bus disposed above the trenches;

depositing an oxide layer uniformly over all exposed surfaces of said multiple trenches and said top surface of said substrate;

depositing a conductive layer in the trenches and over the surface;

patterning the conductive layer remove selected portions to expose portions of the substrate, to form a gate bus over the trenches and to form one or more gates over other portions of the substrate;

implanting the substrate with first and second implants of opposite conductivities for form double diffused well and source regions in exposed portions of the substrate;

depositing a dielectric layer over the substrate;

forming source contact openings in the dielectric layer;

depositing a top metal over said dielectric layer to contact the exposed sources.

2. The process as claimed in claim 1, wherein the step of forming said gate bus trenches comprises forming at least four trenches and wherein said multiple trenches are separated by a predetermined width.

3. The process as claimed in claim 2, wherein said predetermined width is sufficient to create trench field coupling to thereby provide an extended space charge boundary.

4. The process as claimed in claim 1 wherein said step of implanting comprises implanting P type ions to form P wells and implanting N type ions in the P wells to form sources.

5. The process of claim 1 wherein the conductive material comprises doped polysilicon.

6. The process of claim 1 wherein the substrate comprises an epitaxial layer for receiving the trenches.