Microelectronic interconnect material with adhesion promotion layer and fabrication method

• US 20020102838A1
• Filed: 01/30/2002
• Published: 08/01/2002
• Est. Priority Date: 12/22/1998
• Status: Active Grant

• Current Assignee: CVC Products, Inc. (Veeco Instruments Incorporated)
• Original Assignee: CVC Products, Inc. (Veeco Instruments Incorporated)
• Inventors: Velo, Lino A., Campbell, David R. Sr., Leet, David M., Relja, Boris, Moslehi, Mehrdad M., Gopinath, Sanjay, Paranjpe, Ajit P., Bubber, Randhir S., Omstead, Thomas R.
• Granted Patent: US 6,645,847 B2
• Time in Patent Office: Days
• US Class Current: 438/622
• CPC Class Codes: H01L 21/2855 by physical means, e.g. sputtering, evaporation H01L21/28518 - H01L21/28537 and H01L21/28568 take precedence
• CPC Class Codes: H01L 21/28556 by chemical means, e.g. CVD, LPCVD, PECVD, laser CVD H01L21/28518 - H01L21/28537 and H01L21/28568 take precedence
• CPC Class Codes: H01L 21/28568 the conductive layers comprising transition metals H01L21/28518 takes precedence
• CPC Class Codes: H01L 21/76843 formed in openings in a dielectric
• CPC Class Codes: H01L 21/76846 Layer combinations
• CPC Class Codes: H01L 21/76856 by treatment in plasmas or gaseous environments, e.g. nitriding a refractory metal liner
• CPC Class Codes: H01L 21/76876 for deposition from the gas phase, e.g. CVD
• CPC Class Codes: H01L 21/76877 Filling of holes, grooves or trenches, e.g. vias, with conductive material
• CPC Class Codes: H01L 23/53238 Additional layers associated with copper layers, e.g. adhesion, barrier, cladding layers
• CPC Class Codes: H01L 23/53295 Stacked insulating layers
• CPC Class Codes: H01L 2924/00 Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
• CPC Class Codes: H01L 2924/0002 Not covered by any one of groups H01L24/00, H01L24/00 and H01L2224/00

Abstract

A microelectronic semiconductor interconnect structure barrier and method of deposition provide improved conductive barrier material properties for high-performance device interconnects. The barrier includes a refractory metal such as cobalt, cobalt-based alloys, ruthenium or ruthenium-based alloys for promoting adhesion of copper. The barrier materials can be deposited by chemical-vapor deposition to achieve good step coverage and a relatively conformal thin film with a good nucleation surface for subsequent metallization such as copper metallization. In one embodiment, the barrier suppresses diffusion of copper into other layers of the device, including the inter-metal dielectric, pre-metal dielectric, and transistor structures.

Claims

1. A method for fabrication of a microelectronic device on a substrate, the method comprising:

depositing a barrier layer on the substrate, the barrier layer operable to limit diffusion of copper to the substrate;

depositing a cobalt layer over the barrier layer; and

depositing a copper layer over the cobalt layer, the copper layer deposited with a chemical vapor deposition precursor.

2. The method of claim 1 wherein depositing a copper layer further comprises depositing the copper layer with a metal-organic precursor.

3. The method of claim 2 wherein depositing the cobalt layer further comprises depositing the cobalt layer with a chemical vapor deposition precursor.

4. The method of claim 3 wherein the cobalt chemical vapor deposition precursor comprises Co(CO)₃NO.

5. The method of claim 3 wherein the cobalt chemical vapor deposition precursor comprises Co₂(CO)8.

6. The method claim 3 wherein depositing the barrier layer further comprises depositing the barrier layer with a chemical vapor deposition precursor.

7. The method of claim 6 further comprising:

co-depositing the barrier layer and the cobalt layer by flowing the cobalt precursor with the barrier precursor and then ending the barrier precursor flow.

8. The method of claim 7 wherein the barrier layer comprises TaN and the cobalt precursor comprises Co(CO)₃NO.

9. The method of claim 8 further comprising:

co-depositing the cobalt layer and the copper layer by flowing the copper precursor with the cobalt precursor and then ending the cobalt precursor flow.

10. The method of claim 9 wherein the cobalt precursor comprises Co₂ (CO)₈.

11. The method of claim 6 further comprising:

co-depositing the cobalt layer and the copper layer by flowing the copper precursor with the cobalt precursor and then ending the cobalt precursor flow.

12. The method of claim 9 wherein the cobalt precursor comprises Co₂ (CO)₈.

13. The method of claim 2 wherein the microelectronic device comprises an integrated circuit interconnect structure.

15. The method of claim 14 further comprising:

overlapping the flows of the barrier precursor and the cobalt precursor to deposit a graded composition of barrier material and cobalt between the barrier material and the cobalt material.

16. The method of claim 15 further comprising:

overlapping the flows of the cobalt precursor and the copper precursor to deposit a graded composition of cobalt and copper between the cobalt material and the copper material.

17. The method of claim 14 further comprising:

overlapping the flows of the cobalt precursor and the copper precursor to deposit a graded composition of cobalt and copper between the cobalt material and the copper material.

18. The method of claim 17 further comprising:

overlapping the flows of the barrier precursor and the cobalt precursor to deposit a graded composition of barrier material and cobalt between the barrier material and the cobalt material;

wherein the cobalt precursor comprises a first precursor for overlapping with the barrier precursor and a second precursor for overlapping with the copper precursor.

19. The method of claim 18 wherein the barrier material comprises TaN, the first cobalt precursor comprises Co(CO)₃NO and the second cobalt precursor comprises Co₂(CO)₈.

20. The method of claim 19 wherein the copper precursor comprises a metal-organic precursor.

21. The method of claim 14 wherein the electronic device comprises an integrated circuit.

22. The method of claim 21 wherein the structure comprises a copper interconnect.

14. A method for fabricating an electronic device on a semiconductor substrate, the electronic device having a conductive copper structure, the method comprising:

flowing a barrier precursor over the substrate to deposit a barrier material on the substrate, the barrier material reducing diffusion of copper into the substrate;

flowing a cobalt precursor over the substrate to deposit cobalt on the barrier material; and

flowing a copper precursor over the substrate to deposit copper on the cobalt.