Microprocessor with integrated interfaces to system memory and multiplexed input/output bus

• US 20020103988A1
• Filed: 03/22/2002
• Published: 08/01/2002
• Est. Priority Date: 12/18/1996
• Status: Abandoned Application

• Current Assignee: Pascal Dornier
• Original Assignee: Pascal Dornier
• Inventors: Dornier, Pascal
• Application Number:
  US10/104,882
• Publication Number:
  US 20020103988A1
• Time in Patent Office: Days
• US Class Current: 712/38
• CPC Class Codes: G06F 13/4004 Coupling between buses
• CPC Class Codes: Y02D 10/00 Energy efficient computing, e.g. low power processors, power management or thermal management

Abstract

A single-chip IC device has an on-board CPU, an I/O bus controller, and a memory controller all implemented in semiconductor devices on the chip. The CPU, I/O bus controller, and memory controller are interconnected on the IC chip by a parallel data and address bus formed by the IC manufacturing techniques of deposition, patterning, and etching. In a preferred embodiment the on-board local bus has 32 address and 32 data lines. Also in a preferred embodiment the I/O bus controller has 32 data and address paths off the die for connection to a multiplexed I/O bus. The memory controller in the same embodiment has 32 data and 11 address paths off the die to a memory bus with 43 data and address lines. The I/O bus controller is configured to rout memory requests from peripheral devices through the memory controller directly to system memory.

Claims

1. A single-chip IC device comprising:

CPU means for performing digital arithmetical and logical processes;

multiplexing I/O bus controller means for managing address and data communication to first external leads to an I/O bus;

memory controller means for managing address and data communication to second external leads to a memory bus for communicating with one or more random access memory devices; and

local bus means formed on said single-chip IC device for providing communication in parallel between said CPU means, said I/O bus controller means, and said memory controller means;

said I/O bus controller means configured to route memory requests from I/O devices through said memory controller means directly to said one or more random access memory devices.

2. A single-chip device as in claim 1 wherein said memory controller means further comprises a data buffer.

3. A single-chip device as in claim 1 wherein said local bus means is configured to communicate 32-bit data and address words in parallel fashion.

4. A single-chip device as in claim 1 wherein said first external leads are configured to communicate either address or data in up to 32-bit length in parallel.

5. A single-chip device as in claim 1 wherein said second external leads are configured to communicate 32-bit data words and up to 12 address bits.

10. A computer motherboard as in claim 1 wherein said second external leads are configured to communicate 32-bit data words and up to 12 address bits.

6. A computer motherboard comprising:

a multiplexed I/O bus having at least one connector for attaching an I/O bus peripheral;

memory bus means connected to system memory on said motherboard; and

a single-chip IC device mounted to said motherboard and connected to said memory bus means and to said multiplexed I/O bus, said single-chip I/O device comprising;

CPU means for performing digital arithmetical and logical processes;

multiplexing I/O bus controller means for managing address and data communication to first external leads connected to said multiplexed I/O bus;

memory controller means for managing address and data communication to second external leads connected to said memory bus means; and

local bus means formed on said single-chip IC device for providing communication in parallel between said CPU means, said I/O bus controller means, and said memory controller means;

said I/O bus controller means configured to route memory requests from I/O devices through said memory controller means directly to said system memory.

7. A computer motherboard as in claim 6 wherein said memory controller means further comprises a data buffer.

8. A computer motherboard as in claim 6 wherein said local bus means is configured to communicate 32-bit data and address words in parallel fashion.

9. A computer motherboard as in claim 6 wherein said first external leads are configured to communicate either address or data in up to 32-bit length in parallel.

11. A computer motherboard as in claim 6 wherein said system memory comprises DRAM system memory and SRAM cache memory each communicating on said memory bus means.

12. A computer system comprising:

input means for receiving data and commands from a user;

display means for providing text and graphic output to the user; and

a computer motherboard comprising;

a multiplexed I/O bus having at least one connector for attaching an I/O bus peripheral;

memory bus means connected to system memory implemented as at least one IC package mounted to said motherboard; and

a single-chip IC device mounted to said motherboard and connected to said memory bus means and to said multiplexed I/O bus, said single-chip I/O device comprising;

CPU means for performing digital arithmetical and logical processes;

multiplexing I/O bus controller means for managing address and data communication to first external leads connected to said multiplexed I/O bus;

memory controller means for managing address and data communication to second external leads connected to said memory bus means; and

local bus means formed on said single-chip IC device for providing communication in parallel between said CPU means, said I/O bus controller means, and said memory controller means;

said I/O bus controller means configured to route memory requests from I/O devices through said memory controller means directly to said system memory.