Semiconductor test system and method for effectively testing a semiconductor device having many pins
First Claim
1. A semiconductor device test system comprising:
- a plurality of comparator and driver units, each comparator and driver unit comprising a driver configured to drive an input signal pattern to be applied to one or more input pins of the semiconductor device and a comparator configured to compare data output from one or more output pins of the semiconductor device with a predetermined output signal pattern;
a plurality of control units, each control unit configured to electrically connect a corresponding comparator and driver unit to a pin of the semiconductor device in response to a control signal, wherein pins of the semiconductor device are divided into pin groups, each pin group having K number of pins, where K is an integer greater than 1; and
a pattern memory for storing the input signal patterns and the output signal patterns.
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Abstract
According to various aspects and embodiments of this invention, a semiconductor device having many pins can effectively be tested using a test system having fewer pins. A semiconductor device test system and method are provided to effectively test a semiconductor device having many pins. The test system includes a pin electronics (PE) card and a pattern memory. The PE card preferably includes a plurality of comparator and driver units, wherein each comparator and driver unit can include a driver for driving a predetermined input signal pattern to be applied to an input pin of the semiconductor device and a comparator for comparing data output from an output pin of the semiconductor device with a predetermined output signal pattern. Some or all of the pins of the semiconductor device are divided into pin groups having K number of pins. The PE card also preferably includes a plurality of control units for electrically connecting each of the comparator and driver units to a selected pin in a selected pin group of the semiconductor device in response to a control signal. A pattern memory can be used to store input signal patterns and output signal patterns.
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Citations
20 Claims
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1. A semiconductor device test system comprising:
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a plurality of comparator and driver units, each comparator and driver unit comprising a driver configured to drive an input signal pattern to be applied to one or more input pins of the semiconductor device and a comparator configured to compare data output from one or more output pins of the semiconductor device with a predetermined output signal pattern;
a plurality of control units, each control unit configured to electrically connect a corresponding comparator and driver unit to a pin of the semiconductor device in response to a control signal, wherein pins of the semiconductor device are divided into pin groups, each pin group having K number of pins, where K is an integer greater than 1; and
a pattern memory for storing the input signal patterns and the output signal patterns. - View Dependent Claims (2, 3, 4, 5, 6, 7)
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8. A method of testing a semiconductor device, the method comprising:
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selecting pins from among a plurality of pins of the semiconductor device;
dividing the selected pins into a plurality of pin groups, each pin group comprising a desired plural number of pins;
generating a control signal;
electrically connecting a comparator and driver unit to a pin in a corresponding one of the pin groups of the semiconductor device according to the control signal;
applying input signal patterns from an input pattern memory to input pins of the semiconductor device; and
comparing data output from output pins of the semiconductor device with output signal patterns output from an output pattern memory. - View Dependent Claims (9, 10, 11, 13, 14, 15, 17, 18, 19, 20)
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12. A pattern memory for use in a semiconductor device test system, said pattern memory comprising:
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an input pattern memory; and
an output pattern memory, wherein one or more signal patterns are loaded into the pattern memory based on a control signal.
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16. A method of testing a semiconductor device having many pins using a test system having fewer pins, said method comprising:
selectively connecting a pin of the test system to a pin of the semiconductor device based on a control signal.
Specification