Nov-volatile semiconductor memory cell utilizing poly-edge discharge

• US 20020105023A1
• Filed: 05/18/2001
• Published: 08/08/2002
• Est. Priority Date: 02/02/2001
• Status: Active Grant

• Current Assignee: Macronix International Co., Ltd.
• Original Assignee: Macronix International Co., Ltd.
• Inventors: Lung, Hsiang Lan, Kuo, Tung Chen
• Granted Patent: US 6,894,340 B2
• Time in Patent Office: Days
• US Class Current: 257/318
• CPC Class Codes: H01L 29/66833 with a charge trapping gate insulator, e.g. MNOS transistors
• CPC Class Codes: H01L 29/792 with charge trapping gate insulator, e.g. MNOS-memory transistors

Abstract

A process and structure for fabricating a non-volatile memory cell through the formation of a source and drain region and a charge trapping layer located therebetween is presented. E-fields for generating trapped charges are formed through using poly-edge discharge techniques wherein the gate structures of the memory cells are laterally separated from the vertical region of the source and drain regions. The gate structure forms a laterally directed e-field through the charge trapping layer to one of the source and drain regions which enables the charge to be trapped and retained in an area that is lateral to the source and drain regions. Lateral separation of the gate from the source and drain regions is maintained through the use of spacers which may take the form of insulated polysilicon structures or in an alternate embodiment may take the form of insulating spacers located on the sidewalls of the gate structure.

Claims

1. A process for fabricating a non-volatile memory cell, comprising:

a. forming a source region and a drain region on a semiconductor substrate;

b. forming a charge trapping layer at least partially between said source and drain regions for trapping and retaining charge in a trapping region of said charge trapping layer lateral to and between said drain and source regions; and

c. forming a gate on at least a portion of said charge trapping layer, said gate having an edge discharge portion lateral to one of said source and drain regions for inducing said charge with said one of said source and drain regions.

2. The process for fabricating a non-volatile memory cell, as recited in claim 1, further comprising:

a. forming a first lateral spacer extending laterally beyond one of said source and drain regions between said gate and said charge trapping layer for offsetting said edge discharge portion of said gate from said one of said source and drain regions.

3. The process for fabricating a non-volatile memory cell, as recited in claim 2, wherein said first lateral spacer is comprised of polysilicon insulated from said gate.

4. The process for fabricating a non-volatile memory cell, as recited in claim 1, further comprising:

a. forming a first spacer on a sidewall of said gate between said gate and one of said source and drain regions, said first spacer extending laterally between said gate and said one of said source and drain regions on top of said charge trapping layer.

5. The process for fabricating a non-volatile memory cell, as recited in claim 4, wherein said first spacer is comprised of nonconductive oxide.

6. The process for fabricating a non-volatile memory cell, as recited in claim 4, further comprising:

a. forming a first spacer on a first sidewall of said gate extending from said first sidewall of said gate to one of said source and drain regions; and

b. forming a second spacer on a second sidewall of said gate extending from said second sidewall of said gate to the other one of said source and drain regions, said first and second spacers and said gate extending between said source and drain regions.

7. A process for fabricating a non-volatile memory cell, comprising:

a. forming a source region and a drain region on a semiconductor substrate having a channel therebetween;

b. forming a charge trapping layer over at least a portion of said channel; and

c. forming a gate on said charge trapping layer between said source region and said drain region, said gate being shorter in length than the distance between said source region and said drain region.

8. The process for fabricating a non-volatile memory cell, as recited in claim 7, further comprising:

a. forming a first spacer and a second spacer on opposing sidewalls of said gate, said first and second spacers and said gate extending between said source region and said drain region.

9. The process for fabricating a non-volatile memory cell, as recited in claim 8, wherein said first spacer and said second spacer are comprised of nonconductive oxide material.

10. The process for fabricating a non-volatile memory cell, as recited in claim 7, wherein said charge trapping layer includes a bottom layer of silicon dioxide formed over said source region and said drain region, a layer of silicon nitride formed on said bottom silicon dioxide layer, and a top layer of silicon dioxide formed on said nitride layer.

11. A programmable memory cell, comprising:

a. a semiconducting substrate;

b. a source region doped to have a conductivity type opposite of said substrate;

c. a drain region spaced a distance from said source region forming a channel therebetween, said drain region doped to have a conductivity type opposite of said substrate;

d. a charge trapping layer at least partially between said source and drain regions for trapping and retaining charge in a trapping region lateral to and between said drain and source regions; and

e. a gate on at least a portion of said charge trapping layer, said gate having an edge discharge portion lateral to one of said source and drain regions for inducing said charge with said one of said source and drain regions for trapping at least a portion of said charge in said charge trapping layer lateral to said one of said source and drain regions.

12. The programmable memory cell, as recited in claim 11, further comprising

a. a first lateral spacer between said gate and said charge trapping layer for offsetting in a lateral direction said edge discharge portion of said gate from said one of said source and drain regions.

13. The programmable memory cell, as recited in claim 12, wherein said first lateral spacer is comprised of polysilicon insulated from said gate.

14. The programmable memory cell, as recited in claim 11, further comprising:

a. a first spacer between said gate and one of said source and drain regions, said first spacer extending laterally between said gate and said one of said source and drain regions on top of said charge trapping layer.

15. The programmable memory cell, as recited in claim 11, further comprising:

a. forming a first spacer on a first sidewall of said gate extending from said first sidewall of said gate to one of said source and drain regions; and

b. forming a second spacer on a second sidewall of said gate extending from said second sidewall of said gate to the other one of said source and drain regions.

17. The programmable memory cell, as recited in claim 16, further comprising:

a. a first spacer on a first sidewall of said gate extending from said first sidewall of said gate to one of said source and drain regions.

18. The programmable memory cell, as recited in claim 17, further comprising:

a. a second spacer on a second sidewall of said gate extending from said second sidewall of said gate to the other one of said source and drain regions.

19. The programmable memory cell, as recited in claim 18, wherein said first spacer and said second spacer are comprised of nonconductive oxide material.

20. The programmable memory cell, as recited in claim 16, wherein said charge trapping layer includes a bottom layer of silicon dioxide formed over said source region and said drain region, a layer of silicon nitride formed on said bottom silicon dioxide layer, and a top layer of silicon dioxide formed on said nitride layer.

16. A programmable memory cell, comprising:

a. a semiconducting substrate;

b. a source region doped to have a conductivity type opposite of said substrate;

c. a drain region spaced a distance from said source region forming a channel therebetween, said drain region doped to have a conductivity type opposite of said substrate;

d. a charge trapping layer extending between said source region and said drain region, said charge trapping layer fir trapping and retaining charge in a first trapping region lateral to said source region and a second trapping region lateral to said drain region; and

e. a gate on at least a portion of said charge trapping layer, said gate having a first edge discharge portion lateral to said source region and a second edge discharge portion lateral to said drain region, said first and second edge portions for inducing charge with said source and drain regions for trapping in said first and second charge regions in said trapping layer.