Integrated circuit having tap cells and a method for positioning tap cells in an integrated circuit

• US 20020105049A1
• Filed: 02/07/2001
• Published: 08/08/2002
• Est. Priority Date: 02/07/2001
• Status: Active Grant

• Current Assignee: Hewlett-Packard Development Company, L.P. (HP Inc.)
• Original Assignee: Hewlett-Packard Development Company, L.P. (HP Inc.)
• Inventors: Barney, Clive Alva, Grange, Scott Ryan
• Granted Patent: US 6,560,753 B2
• Time in Patent Office: Days
• US Class Current: 257/511
• CPC Class Codes: G06F 30/39 Circuit design at the physical level physical level design for reconfigurable circuits G06F30/347
• CPC Class Codes: H01L 27/118 Masterslice integrated circuits

Abstract

An integrated circuit includes a set of standard cells, referred to as tap cells, each having a well tap and a substrate tap for coupling a well region and a substrate region to a power source and ground, respectively. The tap cells are disposed at intervals that do not exceed a maximum allowable distance as specified by a set of design rules associated with the integrated circuit. A method for designing the integrated circuit includes determining the positions at which the tap cells will be fixed and creating a design layout for the integrated circuit using a place and route tool that incorporates the positions.

Claims

1. An integrated circuit comprising:

a plurality of tap cells, each tap cell including at least one of a well tap and a substrate tap, wherein said tap cells are fixed at intervals, and further wherein said intervals do not exceed a maximum allowable distance.

2. The integrated circuit as defined in claim 1 wherein said intervals are generally equally spaced

3. The integrated circuit as defined in claim 1 wherein each tap cell comprises a well tap and a substrate tap, said well tap being disposed in a well region of said tap cell and said substrate tap being disposed in a substrate region of said tap cell.

4. The integrated circuit as defined in claim 1 wherein said integrated circuit is partitioned into a set of rows and further wherein said tap cells are located in alternating rows.

5. The integrated circuit as defined in claim 4 further comprising a set of logic cells configured and adapted to cause said integrated circuit to perform a set of desired functions, wherein said logic cells are disposed in said rows, and further wherein said logic cells disposed in said alternating rows with said tap cells are located in said intervals between said tap cells.

6. The integrated circuit as defined in claim 1 wherein said maximum allowable distance is obtained using a set of design rules associated with said integrated circuit.

7. The integrated circuit as defined in claim 1 wherein said integrated circuit is a CMOS integrated circuit.

8. An integrated circuit comprising:

a placeable area that is partitioned into a set of rows;

a plurality of tap cells disposed in alternating rows of said placeable area, wherein each tap cell includes at least one of a well tap and a substrate tap, and wherein said tap cells are fixed at intervals in said alternating rows, and further wherein said intervals do not exceed a maximum allowable distance;

a plurality of logic cells disposed in said rows of said placeable area, wherein said logic cells are adapted to cause said integrated circuit to perform a set of desired functions, and wherein said logic cells disposed in said alternating rows with said tap cells are positioned in said intervals between said tap cells.

9. The integrated circuit as defined in claim 8 wherein said intervals are generally equally spaced.

10. The integrated circuit as defined in claim 8 wherein said maximum allowable distance is obtained using a set of design rules associated with said integrated circuit.

11. The integrated circuit as defined in claim 8 wherein said integrated circuit is a CMOS integrated circuit.

13. The method as defined in claim 12 wherein said intervals are generally equally spaced.

14. The method as defined in claim 12 wherein said step of creating said layout is performed using a computer-automated design tool.

15. The method as defined in claim 14 wherein said computer-automated design tool comprises a place and route tool.

16. The method as defined in claim 15 wherein said step of creating said layout further comprises the steps of:

modifying a floorplan associated with said integrated circuit to incorporate said positions at which said tap cells will be fixed;

providing said floorplan as data input to said place and route tool; and

,

causing said place and route tool to incorporate said floorplan into said layout.

17. The method as defined in claim 16 wherein said floorplan comprises a set of physical constraints associated with said integrated circuit.

18. The method as defined in claim 16 wherein said step of creating said layout further comprises the steps of:

providing a list of logic cells as data input to said place and route tool, wherein said logic cells are adapted to cause said integrated circuit to perform a set of desired functions; and

,

causing said place and route tool to incorporate said logic cells into said layout.

20. The method as defined in claim 19 wherein said intervals are generally equally spaced.

21. The method as defined in claim 19 wherein said integrated circuit is partitioned into a set of rows and wherein said positions are located in alternating rows.

22. The method as defined in claim 19 wherein said step of providing said positions as data input to a place and route tool further comprises the steps of:

modifying a floorplan associated with said integrated circuit to incorporate said positions at which said tap cells will be fixed; and

,

providing said floorplan as data input to said place and route tool.

23. The method as defined in claim 22 wherein said floorplan comprises a set of physical constraints associated with said integrated circuit.

24. The method as defined in claim 19 wherein said step of using said place and route tool to create said layout further comprises the steps of:

providing a list of logic cells as data input to said place and route tool, wherein said logic cells are adapted to cause said integrated circuit to perform a set of desired functions; and

,

causing said place and route tool to incorporate said logic cells into said layout.

25. The method as defined in claim 24 wherein said integrated circuit is partitioned into a set of rows, and wherein said positions at which said tap cells will be fixed are disposed in alternating rows.

12. A method for designing an integrated circuit, comprising the steps of:

determining a set of positions at which a set of tap cells will be fixed in said integrated circuit, wherein each of said tap cells includes at least one of a well tap and a substrate tap, and wherein said positions are located at intervals, and further wherein said intervals do not exceed a maximum allowable distance; and

,

creating a layout for said integrated circuit, wherein said layout incorporates said positions at which said tap cells will be fixed.

19. A method for designing an integrated circuit, comprising the steps of:

determining a set of positions at which a set of tap cells will be fixed in said integrated circuit, wherein each of said tap cells includes at least one of a well tap and a substrate tap, and wherein said positions are located at intervals, and further wherein said intervals do not exceed a maximum allowable distance;

providing said positions as data input to a place and route tool; and

,

using said place and route tool to create a layout for said integrated circuit, wherein said layout incorporates said positions at which said tap cells will be fixed.