METHOD OF FORMING A DUAL DAMASCENE STRUCTURE BY PATTERNING A SACRIFICIAL LAYER TO DEFINE THE PLUG PORTIONS OF THE STRUCTURE

• US 20020106887A1
• Filed: 05/10/2001
• Published: 08/08/2002
• Est. Priority Date: 02/02/2001
• Status: Active Grant

• Current Assignee: Macronix International Co., Ltd.
• Original Assignee: Macronix International Co., Ltd.
• Inventors: Chang, Ching-Yu
• Granted Patent: US 6,440,842 B1
• Time in Patent Office: Days
• US Class Current: 438/618
• CPC Class Codes: H01L 21/76807 for dual damascene structures
• CPC Class Codes: H01L 21/76885 By forming conductive members before deposition of protective insulating material, e.g. pillars, studs
• CPC Class Codes: H01L 2221/1026 the via being formed by burying a sacrificial pillar in the dielectric and removing the pillar

Abstract

A semiconductor wafer comprises a substrate, and a conductive area positioned on a predetermined area of the substrate. A sacrificial layer is formed on the surface of the substrate. A patterned first photoresist layer is formed on the surface of the sacrificial layer, covering the conductive area, followed by removal of the sacrificial layer not covered by the first photoresist layer. A dielectric layer is formed on the surface of the substrate, and a second photoresist layer is formed on the surface of the dielectric layer. A line-shaped opening is formed in the second photoresist layer, followed by etching portions of the dielectric layer through the line-shaped opening for forming a line-shaped recess. The second photoresist layer and the remaining sacrificial layer are completely removed for forming a plug hole in the bottom of the line-shaped recess. Finally, a metal conductive wire and a conductive plug are formed in the line-shaped recess and in the plug hole, with the metal conductive wire coupled with the conductive plug defining a dual damascene structure.

Claims

1. A method of forming a dual damascene structure on a semiconductor wafer, the semiconductor wafer comprising a substrate and a conductive area positioned on a predetermined area of the substrate, the method comprising:

forming a sacrificial layer on the surface of the substrate that covers the conductive area;

forming a patterned first photoresist layer on the surface of the sacrificial layer, the first photoresist layer positioned above the conductive area;

performing a first dry-etching process to remove the sacrificial layer not covered by the first photoresist layer;

removing the first photoresist layer;

forming a dielectric layer on the surface of the substrate that covers the remaining sacrificial layer;

forming a second photoresist layer on the surface of the dielectric layer;

performing a lithography process to form a line-shaped opening in the second photoresist layer positioned above the remaining sacrificial layer;

performing a second dry-etching process to etch portions of the dielectric layer through the line-shaped opening to form a line-shaped recess, the remaining sacrificial layer protruding from a bottom surface of the line-shaped recess;

removing the second photoresist layer and the remaining sacrificial layer to form a plug hole in the bottom of the line-shaped recess;

forming a metal layer on the surface of the semiconductor wafer that fills the line-shaped recess and the plug hole for respectively forming a metal conductive wire and a conductive plug, the metal conductive wire coupled with the conductive plug defining a dual damascene structure; and

removing the metal layer positioned on a top surface of the dielectric layer.

2. The method of claim 1 comprising a chemical mechanical polishing (CMP) process for leveling the surface of the dielectric layer.

3. The method of claim 1 wherein the method of removing the remaining sacrificial layer is a wet-etching process.

4. The method of claim 3 wherein the sacrificial layer and the dielectric layer are respectively composed of silicon oxide and silicon nitride, and the wet-etching process uses hydrofluoric acid (HF) as an etching solution.

5. The method of claim 3 wherein the sacrificial layer and the dielectric layer are respectively composed of silicon nitride and silicon oxide, and the wet-etching process uses phosphoric acid (H₃PO₄) as an etching solution.

6. The method of claim 1 wherein a chemical mechanical polish (CMP) process is used to remove the metal layer positioned on the top surface of the dielectric layer to align an upper surface of the metal conductive wire with the surface of the dielectric layer.

7. A method of forming a dual damascene structure on a semiconductor wafer, the semiconductor wafer comprising a substrate, a conductive area positioned on a predetermined area of the substrate, and a patterned first photoresist layer positioned on the substrate above the conductive area, the method comprising:

forming a dielectric layer that covers the patterned first photoresist layer, and forming a second photoresist layer positioned on the dielectric layer;

performing a lithography process to form a line-shaped opening in the second photoresist layer positioned above the patterned first photoresist layer;

performing a dry-etching process to etch portions of the dielectric layer through the line-shaped opening to form a line-shaped recess, the patterned first photoresist layer protruding from a bottom surface of the line-shaped recess;

removing the second photoresist layer and the patterned first photoresist layer to form a plug hole in the bottom of the line-shaped recess;

forming a metal layer on the surface of the semiconductor wafer that fills the line-shaped recess and the plug hole for respectively forming a metal conductive wire and a conductive plug, the metal conductive wire coupled with the conductive plug defining a dual damascene structure; and

removing the metal layer positioned on a top surface of the dielectric layer.

8. The method of claim 7 comprising a chemical mechanical polishing (CMP) process for leveling the surface of the dielectric layer.

9. The method of claim 7 wherein a chemical mechanical polishing (CMP) process is used to remove the metal layer positioned on the top surface of the dielectric layer to align an upper surface of the metal conductive wire with the surface of the dielectric layer.

10. The method of claim 7 wherein the dielectric layer is composed of silicon oxide or silicon nitride.

11. A method of forming a dual damascene structure on a semiconductor wafer, the semiconductor wafer comprising a substrate and a conductive area positioned on a predetermined area of the substrate, the method comprising:

forming a conductive layer on the surface of the substrate that covers the conductive area;

forming a patterned first photoresist layer on the surface of the conductive layer, the first photoresist layer positioned above the conductive area;

performing a first dry-etching process to remove the conductive layer not covered by the first photoresist layer;

removing the first photoresist layer;

forming a dielectric layer on the surface of the substrate that covers the remaining conductive layer;

forming a second photoresist layer on the surface of the dielectric layer;

performing a lithography process to form a line-shaped opening in the second photoresist layer positioned above the remaining conductive layer;

performing a second dry-etching process to etch portions of the dielectric layer through the line-shaped opening to form a line-shaped recess, the remaining conductive layer protruding from a bottom surface of the line-shaped recess;

removing the second photoresist layer;

forming a metal layer on the surface of the semiconductor wafer that fills the line-shaped recess for connecting the metal layer and the remaining conductive layer so as to respectively form a metal conductive wire and a conductive plug, the metal conductive wire coupled with the conductive plug defining a dual damascene structure; and

removing the metal layer positioned on the top surface of the dielectric layer.

12. The method of claim 11 wherein the conductive layer is a metal layer or a doped polysilicon layer.

13. The method of claim 11 comprising a chemical mechanical polishing (CMP) process to level the surface of the dielectric layer.

14. The method of claim 11 wherein a chemical mechanical polishing (CMP) process is used to remove the metal layer positioned on the top surface of the dielectric layer to align an upper surface of the metal conductive wire with the surface of the dielectric layer.

15. The method of claim 11 wherein the dielectric layer is composed of silicon oxide or silicon nitride.