Apparatus for establishing an electrical connection with a wafer to facilitate wafer-level burn-in and methods

• US 20020106911A1
• Filed: 11/07/2001
• Published: 08/08/2002
• Est. Priority Date: 02/06/2001
• Status: Active Grant

• Current Assignee: John W. Ladd
• Original Assignee: John W. Ladd
• Inventors: Ladd, John W.
• Granted Patent: US 7,032,288 B2
• Time in Patent Office: Days
• US Class Current: 439/40
• CPC Class Codes: G01R 1/0416 Connectors, terminals G01R1/0425 and G01R1/0433 take precedence; with measurement function for battery poles G01R31/364
• CPC Class Codes: G01R 31/2831 Testing of materials or semi-finished products, e.g. semiconductor wafers or substrates G01R31/318511 takes precedence; testing during manufacture H01L22/00
• CPC Class Codes: G01R 31/2863 Contacting devices, e.g. sockets, burn-in boards or mounting fixtures in general G01R1/04
• CPC Class Codes: G01R 31/3025 Wireless interface with the DUT
• CPC Class Codes: H01R 13/22 Contacts for co-operating by abutting
• CPC Class Codes: H01R 13/6205 Two-part coupling devices held in engagement by a magnet
• CPC Class Codes: H01R 2201/20 for testing or measuring purposes
• CPC Class Codes: Y10T 29/49004 including measuring or testing of device or component part
• CPC Class Codes: Y10T 29/49126 Assembling bases
• CPC Class Codes: Y10T 29/4913 Assembling to base an electrical component, e.g., capacitor, etc.
• CPC Class Codes: Y10T 29/49169 Assembling electrical component directly to terminal or elongated conductor
• CPC Class Codes: Y10T 29/49174 Assembling terminal to elongated conductor
• CPC Class Codes: Y10T 29/49204 Contact or terminal manufacturing

Abstract

An electrical connector configured to nonrigidly apply force to a semiconductor substrate in directions substantially normal to a plane of the semiconductor substrate. The electrical connector includes a first member with an electrically conductive element and a first attractive element and a second member that includes a support element and a second attractive element. Attractive forces, such as magnetic attraction, between the first and second attractive elements secure the first and second members of the electrical connector to the semiconductor substrate in a manner that facilitates communication between the electrically conductive element of the first member and one or more semiconductor devices carried upon the semiconductor substrate. The electrical connector may be used in stress testing of semiconductor devices or to otherwise establish an electrical connection between one or more semiconductor devices, a ground, and a power source.

Claims

1. A method for establishing an electrical contact with at least one semiconductor device, comprising:

establishing an electrical contact between a first member of an electrical connector and a contact that is in electrical communication with the at least one semiconductor device; and

drawing said first member toward said contact.

2. The method of claim 1, wherein said drawing is effected in a direction substantially normal to a plane of said contact.

3. The method of claim 1, wherein said drawing is effected in a direction substantially normal to a plane of a substrate upon which said contact is carried.

4. The method of claim 1, wherein said drawing is effected by positioning a second member of said electrical connector opposite said first member.

5. The method of claim 4, wherein said drawing is effected by magnetically attracting at least one of said first member and said second member toward at least the other of said first member and said second member.

6. The method of claim 4, wherein said drawing comprises securing said first and second members to a substrate upon which said contact is carried.

7. The method of claim 1, wherein said drawing comprises magnetically attracting said first member against said contact.

8. A method for stress testing a plurality of semiconductor devices carried upon a common substrate and in communication with common ground and power contacts, comprising:

establishing electrical contact between a first member of an electrical connector and at least one contact of the ground contact and the power contact; and

drawing said first member toward said at least one contact.

9. The method of claim 8, wherein said drawing is effected in a direction substantially normal to a plane of the substrate.

10. The method of claim 8, wherein said drawing nonrigidly biases said first member against said contact.

11. The method of claim 8, wherein said drawing comprises positioning a second member of said electrical connector opposite the substrate from said first member.

12. The method of claim 11, wherein at least one of said first member and said second member is drawn toward at least the other of said first member and said second member.

13. The method of claim 12, wherein said drawing comprises magnetically attracting at least one of said first member and said second member toward at least the other of said first member and said second member.

14. The method of claim 8, wherein said drawing comprises magnetically attracting said first member against said at least one contact.

15. The method of claim 8, wherein said drawing comprises securing at least said first member in position relative to the substrate.

16. The method of claim 8, further comprising:

electrically connecting another first member of another electrical connector to another of the ground contact and the power contact; and

drawing said another first member toward said another contact.

17. The method of claim 16, further comprising:

applying a substantially constant amount of current to each semiconductor device of the plurality of semiconductor devices through said first member and said another first member.

18. The method of claim 17, further comprising:

heating each of the plurality of semiconductor devices.

19. The method of claim 18, wherein said heating comprises cycling a temperature of each of the plurality of semiconductor devices.

20. The method of claim 18, wherein said heating comprises varying a temperature of each of the plurality of semiconductor devices.