Methods and systems for the order serialization of information in a network processing environment

• US 20020107903A1
• Filed: 03/01/2001
• Published: 08/08/2002
• Est. Priority Date: 11/07/2000
• Status: Abandoned Application

• Current Assignee: Surgient Networks, Inc. (Quest Software, Inc.)
• Original Assignee: Surgient Networks, Inc. (Quest Software, Inc.)
• Inventors: Hernandez, Gustavo G., Richter, Roger K., Wang, Ho
• Application Number:
  US09/797,197
• Publication Number:
  US 20020107903A1
• Time in Patent Office: Days
• US Class Current: 709/201
• CPC Class Codes: H04L 43/00 Arrangements for monitoring or testing data switching networks
• CPC Class Codes: H04L 43/0847 Transmission error
• CPC Class Codes: H04L 43/12 Network monitoring probes
• CPC Class Codes: H04L 67/1001 for accessing one among a plurality of replicated servers
• CPC Class Codes: H04L 67/56 Provisioning of proxy services store-and-forward switching systems in data switching networks H04L12/54
• CPC Class Codes: H04L 67/5651 Reducing the amount or size of exchanged application data
• CPC Class Codes: H04L 69/22 Parsing or analysis of headers
• CPC Class Codes: H04L 69/329 in the application layer [OSI layer 7]
• CPC Class Codes: H04L 9/40 Network security protocols

Abstract

A multi-processor network processing environment is provided in which parallel processing may occur. In one embodiment, a network processor having multiple processor cores may be utilized. Parallel processing at the front end of the network processor is encouraged while still maintaining ordered serialization between the input and the output of the network processor. The disclosed order serialization techniques obtain the benefits of parallel processing at the front end of the system while minimizing blocking times at the output.

Claims

1. A network processing system comprising:

a network processor having a plurality of processing cores, the processing cores operable to process information in a substantially parallel manner; and

a processor value associated with each of the processing cores, the processor value operable to identify each processing core for communicating the information.

2. The system of claim 1, further comprising a processing token operably coupled to the network processor, the processing token including a valid processor value associated with one of the processing cores.

3. The system of claim 2, wherein the processing token comprises a hardware latch deployable by the processing cores.

4. The system of claim 2, wherein the processing token may be updated by a processing core associated with the valid processor value.

5. The system of claim 2, wherein the processing token may be exclusively accessed by a processing core within the network processor.

6. The system of claim 2, wherein the processing token maintains a processing order associated with processing information using the network processor.

7. The system of claim 2, further comprising memory operably coupled to the network processor, the memory operable to store the processor values associated with each of the processing cores.

8. The system of claim 7, wherein the memory comprises the processing token.

9. The system of claim 7, wherein the memory comprises a list of the processor values, the list having a reference identifying the valid processor value.

10. The system of claim 1, further comprising plural network processors operably coupled to the network processor.

11. The system of claim 10, wherein the plural network processors comprise distributed network processors.

12. The system of claim 1, wherein the processing cores comprise processes operably associated with the network processor.

14. The method of claim 13, wherein the processing further comprises:

accessing a processing input queue including data packets; and

dequeueing at least one data packet from the processing input queue.

15. The method of claim 13, further comprising accessing a processing token associated with providing the valid processor value.

16. The method of claim 15, further comprising latching the processing token to determine the valid processing value.

17. The method of claim 16, further comprising releasing the processing token upon determining the valid processor value.

18. The method of claim 16, further comprising:

updating the processing token to a next processor value; and

releasing the processing token.

19. The method of claim 18, further comprising:

queuing the information within an output queue; and

communicating the information from the output queue to a communication medium.

20. The method of claim 18, further comprising:

dequeueing the information from an input queue; and

processing the information using the processing core.

13. A method for processing information in a network environment comprising:

processing information using a network processor having a plurality of processing cores;

determining a valid processor value operably associated with communicating the information; and

communicating the processed information from the network processor in response to determining the valid processor value.

21. A parallel network processing system comprising:

a plurality of processing cores operable to process information in a substantially parallel manner;

a processor value associated with each of the processing cores, the processor value identifying each processing core;

a processing token operably associated with the processing cores, the processing token operable to identify a processing core to communicate information;

wherein the processing token is operable to be updated by a valid processing core; and

output memory coupled to the plurality of processing cores, the output memory operable to store the information based on the valid processing core.

22. A method of operating a network processor comprising

providing a plurality of processor cores within the network processor;

receiving multiple incoming data packets within the network processor;

performing parallel processing on at least a portion of the data packets with the multiple processor cores, the processing times for a plurality of the incoming data packets varying;

providing processor core processing output results which are to be forwarded for additional processing; and

maintaining order serialization of the processor core output results with respect to the order of the multiple incoming data packets,

wherein the order serialization is maintained even though the processing times vary.

23. The method of claim 22, the maintaining step comprising determining if an individual processor core is a currently valid processor core.

24. The method of claim 23, further comprising stalling the processing of one of the processor cores if the processor core is not a currently valid processor core.

25. The method of claim 23, further comprising processing additional data in one of the processor cores if the processor core is not a currently valid processor core.

26. The method of claim 22, wherein the order serialization is performed by accessing a processor output token.

27. The method of claim 26, further comprising inhibiting changes by one processor core to the processor output token when another one processor core is accessing the processor output token.

28. The method of claim 27, further comprising latching the processor output token to achieve the inhibiting.

29. The method of claim 27, further comprising utilizing a currently valid processor core to update the processor output token.

30. The method of claim 26, further comprising utilizing a currently valid processor core to update the processor output token.

31. The method of claim 30, wherein a static sequence is utilized to order serialize the output results.

32. The method of claim 30, wherein a dynamic sequence is utilized to order serialize the output results.

33. The method of claim 22, wherein a static sequence is utilized to order serialize the output results.

34. The method of claim 33, wherein the static sequence is a logical based sequence.

35. The method of claim 34, wherein the static sequence is a round robin sequence.

36. The method of claim 34, wherein the sequence is a defined list sequence.

37. The method of claim 22, wherein a dynamic output sequence is utilized to order serialize the output results.

39. The method of claim 38, the providing step comprising determining if an individual processor core is a currently valid processor core.

40. The method of claim 39, further comprising stalling the processing of one of the processor cores if the processor core is not a currently valid processor core.

41. The method of claim 39, further comprising processing additional data in one of the processor cores if the processor core is not a currently valid processor core.

42. The method of claim 38, wherein the order serialization is performed by accessing a processor output token.

43. The method of claim 42, further comprising inhibiting changes by one processor core to the processor output token when another one processor core is accessing the processor output token.

44. The method of claim 43, further comprising latching the processor output token to achieve the inhibiting.

45. The method of claim 43, further comprising utilizing a currently valid processor core to update the processor output token.

46. The method of claim 42, further comprising utilizing a currently valid processor core to update the processor output token.

47. The method of claim 42, wherein processing times for the plurality of processor cores to process the data packets varies.

48. The method of claim 42, wherein a static sequence is utilized to order serialize the output results.

49. The method of claim 48, wherein the static sequence is a logical based sequence.

50. The method of claim 49, wherein the static sequence is a round robin sequence.

51. The method of claim 49, wherein the sequence is a defined list sequence.

52. The method of claim 42, wherein a dynamic sequence is utilized to order serialize the output results.

53. The method of claim 38, wherein a static output sequence is utilized to order serialize the output results.

54. The method of claim 38, wherein a dynamic output sequence is utilized to order serialize the output results.

38. A method of operating a network endpoint system, comprising:

providing a processor engine, the processor engine comprising a plurality of processor cores;

receiving an incoming data stream from a network connection;

assigning portions of the incoming data stream to the plurality of processor cores for processing;

processing the portions of the incoming data stream within the processor cores to provide output data which is to further processed by other resources of the network endpoint system; and

providing the output data from the processor cores in an order serialized manner which corresponds order of the incoming data streams.

55. A method of operating a network processor comprising:

receiving input data by the network processor in the form of a plurality of data packets to be processed at least in part by the network processor, the network processor providing output data to be subject to additional processing;

assigning the data packets to multiple processor cores within the network processor so that parallel processing of the data packets may be performed;

processing the data packets at least in part with the processor cores;

determining if output results of an individual processor core may be provided for further processing, the determining being based upon an output sequence; and

providing the output results of the individual processor core based upon the determining step,

wherein the output results of a plurality of the processor cores are provided in an output order corresponding to the order of the input data.

56. The method of claim 55, the determining step comprising determining if the individual processor core is a currently valid processor core.

57. The method of claim 56, further comprising stalling the processing of one of the processor cores if the processor core is not a currently valid processor core.

58. The method of claim 56, further comprising processing additional data in one of the processor cores if the processor core is not a currently valid processor core.

59. The method of claim 55 wherein the ordering is performed by accessing a processor output token.

60. The method of claim 59, further comprising inhibiting changes by one processor core to the processor output token when another one processor core is accessing the processor output token.

61. The method of claim 60, further comprising latching the processor output token to achieve the inhibiting.

62. The method of claim 60, further comprising utilizing a currently valid processor core to update the processor output token.

63. The method of claim 59, further comprising utilizing a currently valid processor core to update the processor output token.

64. A method of operating a network processor comprising:

receiving incoming data packets in an incoming data order;

processing incoming data packets in a parallel processing manner with a plurality of processor cores within the network processor;

generating processing results with the processor cores, the processor results for a plurality of the incoming data packets being generated in a time order that varies from the incoming data order; and

order serializing the output results provided from the plurality of processor cores, the order serialization being with respect to the incoming data order; and

forwarded the output results so that additional processing may be performed upon the output results.

65. The method of claim 64, wherein the processing times for the plurality of processor cores to process the data packets varies.

66. The method of claim 64, wherein a static sequence is utilized to order serialize the output results.

67. The method of claim 66, wherein the static sequence is a logical based sequence.

68. The method of claim 67, wherein the static sequence is a round robin sequence.

69. The method of claim 66, wherein the sequence is a defined list sequence.

70. The method of claim 64, wherein a dynamic sequence is utilized to order serialize the output results.

71. A method of configuring an endpoint system, comprising:

providing a network interface processing engine to receive an incoming data stream from a network;

providing a plurality of processor cores with the network interface processing engine;

providing at least one system processing engine to perform endpoint functions in response to the incoming data stream;

providing an interconnection coupling the network interface processing engine and the at least one system processing engine;

processing the incoming data stream with the plurality of processor cores in a parallel manner;

generating processor results from the incoming data stream in the plurality of processor cores in a time sequence that does not correspond to an input sequence of the incoming data stream; and

ordering an output sequence of the processor results from the plurality of processor cores such that a network interface processing engine output data stream is order serialized with respect to the input sequence of the incoming data stream.

72. The method of claim 71, wherein the processing times for the plurality of processor cores to process the data packets varies.

73. The method of claim 71 wherein the output sequence is a static sequence.

74. The method of claim 73, wherein the static sequence is a logical based sequence.

75. The method of claim 74, wherein the static sequence is a round robin sequence.

76. The method of claim 73, wherein the sequence is a defined list sequence.

77. The method of claim 71, wherein the sequence is a dynamic sequence.

78. The method of claim 71 wherein the ordering is performed by accessing a processor output token.

79. The method of claim 71, the ordering step further comprising determining, when processing results are available from one of the processor cores, if that processor core is a currently valid processor core.

80. The method of claim 79, further comprising stalling the processing of one of the processor cores if the processor core is not a currently valid processor core.

81. The method of claim 79, further comprising processing additional data in one of the processor cores if the processor core is not a currently valid processor core.

82. A network processor, comprising:

an input, the input provided to receive an input data stream;

a plurality of processor cores, the processor cores be configured to process data packets and then forward the data packets for additional processing, the processor cores coupled to the input; and

a processor output token coupled to the plurality of processor cores so that the plurality of processor cores utilize the processor output token to determine an output sequence for the processor cores,

wherein the output sequence of the processor cores is order serialized with respect to the input data stream.

83. The network processor of claim 82, wherein the processing times for the plurality of processor cores to process the data packets varies.

84. The network processor of claim 82 wherein the output sequence is a static sequence.

85. The network processor of claim 84, wherein the static sequence is a logical based sequence.

86. The network processor of claim 85, wherein the static sequence is a round robin sequence.

87. The network processor of claim 84, wherein the sequence is a defined list sequence.

88. The network processor of claim 87, wherein the processor output token comprises memory fields containing processor core identifiers.

89. The network processor of claim 88, wherein the processor output token further comprises a field identifier.

90. The network processor of claim 89, wherein the field identifier is a pointer.

91. The network processor of claim 89, wherein the field identifier is an index.

92. The network processor of claim 82, wherein the sequence is a dynamic sequence.

93. The network processor of claim 92, wherein the processor output token comprises a queue containing processor core identifiers.

94. The network processor of claim 93, wherein the queue size may vary.

95. A network connectable computing system, the system being configured to be connected on at least one end to a network, the system comprising:

a network interface engine comprising at least one network processor having a plurality of processor cores, the network interface engine coupling an input data stream from the network to the computing system;

at least one system processor engine providing system functionality processing; and

a distributed interconnection between the at least one system processor engine and the network interface engine,

wherein processor results from the plurality of processor cores are provided in a time sequence that is different from an input sequence of the incoming data stream; and

order serialization is applied within the network interface engine such that a network interface processing engine output data stream is order serialized with respect to the input sequence of the incoming data stream.

96. The system of claim 95, wherein the network processor analyzes headers of the data packets provided to the computing system.

97. The system of claim 95, wherein the system is an intermediate network node system.

98. The system of claim 97, wherein the system is a network switch.

99. The system of claim 95, wherein the system is a network endpoint system.

100. The system of claim 95, wherein the system is a network endpoint system having at least one server or at least one server card.

101. The system of claim 95, wherein the system is incorporated into a network interface card.

102. The system of claim 100, wherein the system is a content delivery system.

103. The system of claim 102, wherein the distributed interconnection is a switch fabric.

104. The system of claim 95, wherein system is an asymmetric multi-processing system having a plurality of system processor engines.

105. The system of claim 95, wherein the plurality of system processor engines are configured to perform separate tasks.

106. The system of claim 105, wherein the distributed interconnection is a switch fabric and the task specific processor engines include storage or application processor engines.

107. The system of claim 106, wherein the task specific processor engines include storage and application processors.