System and method for optimizing power/performance in network-centric microprocessor-controlled devices

• US 20020108064A1
• Filed: 02/07/2001
• Published: 08/08/2002
• Est. Priority Date: 02/07/2001
• Status: Abandoned Application

• Current Assignee: Patrick Nunally
• Original Assignee: Patrick Nunally
• Inventors: Nunally, Patrick
• Application Number:
  US09/779,395
• Publication Number:
  US 20020108064A1
• Time in Patent Office: Days
• US Class Current: 713/300
• CPC Class Codes: G06F 1/3203 Power management, i.e. event-based initiation of a power-saving mode
• CPC Class Codes: G06F 1/324 by lowering clock frequency
• CPC Class Codes: G06F 1/329 by task scheduling
• CPC Class Codes: G06F 9/30083 Power or thermal control instructions
• CPC Class Codes: Y02D 10/00 Energy efficient computing, e.g. low power processors, power management or thermal management

Abstract

A method and system for controlling the speed of a microprocessor in a microprocessor-controlled device when executing an application program retrieved from a remote repository. The program retrieved contains embedded instructions related to the processing power required to execute the program and maintain a specified quality of performance. The processor speed is adjusted consistent with the embedded instructions so that when necessary, the processor can function at a higher speed, consuming greater power, and when not necessary, the processor can return to consuming lower power at a low-speed state, to thereby conserve battery resources.

Claims

1. A method of controlling the operating speed of a microprocessor in a microprocessor-controlled device so that the microprocessor has sufficient processing power to run a program while a predetermined level of performance quality is maintained, comprising:

embedding operating speed instructions in a program to be used by a microprocessor;

executing the program by the microprocessor;

reading the embedded instructions; and

adjusting the operating speed of the microprocessor from a first speed to a second speed in accordance with the instructions such that sufficient processing power is provided to achieve a predetermined level of performance in executing the program.

2. The method of claim 1, wherein the program is downloaded from a remote repository.

3. The method of claim 1, wherein the program is downloaded over a network.

4. The method of claim 1, wherein the program is downloaded over the Internet.

5. The method of claim 1, wherein the program is a Java applet.

6. The method of claim 5, where the embedded instructions are read by a Java Virtual Machine.

7. The method of claim 1, wherein the instructions are read by a hardware component.

8. The method of claim 6, wherein the applet contains a multimedia application.

9. The method of claim 1, further comprising returning the operating speed of the microprocessor from the second speed to the first speed after the program completes running.

10. The method of claim 1, wherein the instructions are embedded by the creator of the program.

11. The method of claim 1, wherein the instructions are embedded by the distributor of the program.

12. The method of claim 1, wherein the instructions are embedded by the recipient of the program.

13. The method of claim 1, wherein the program is stored on a memory card.

14. The method of claim 1, wherein the instructions define a suggested processor speed.

15. The method of claim 14, wherein the instructions bear information used by the processor to optimally execute the program.

16. The method of claim 1, wherein the instructions instruct the microprocessor to alter a clock speed.

17. The method of claim 1, wherein the instructions include a number of instructions per second that that are to be processed.

19. The method of claim 18, wherein the applet is downloaded from a remote repository.

20. The method of claim 18, wherein the instructions instruct the microprocessor to alter a clock speed.

21. The method of claim 18, further comprising returning the operating speed of the microprocessor from the high-speed, high-power setting to the low-speed, low-power setting after execution of the applet.

22. The method of claim 18, wherein the instructions include a number of instructions per second that that are to be processed.

23. The method of claim 19, wherein the instructions bear information used by the processor to optimally execute the program.

25. The system of claim 24, wherein the instructions instruct the microprocessor to alter a clock speed.

26. The system of claim 24, wherein the instructions include a number of instructions per second that that are to be processed.

18. A method of controlling the speed of a microprocessor in a network-centric microprocessor-controlled device so that the microprocessor has sufficient processing power to run an applet while maintaining a predetermined level of performance, comprising:

embedding operating speed instructions in a Java applet to be used by a microprocessor;

executing the applet by a Java Virtual Machine coupled to the microprocessor;

reading the instructions embedded in the applet; and

adjusting the speed of the microprocessor in accordance with the instructions from a low-speed, low-power setting to a high-speed, high-power setting such that sufficient processing power is provided to achieve a predetermined level of performance in executing the applet.

24. A system for controlling the operating speed of a microprocessor so that the microprocessor has sufficient processing power to run a program while a predetermined level of performance quality is maintained, comprising:

means for embedding operating speed instructions in a program to be used by a microprocessor;

means for downloading the program so it can be executed by the microprocessor;

means for reading the embedded instructions; and

means for adjusting the operating speed of the microprocessor from a first speed to a second speed in accordance with the instructions such that sufficient processing power is provided to achieve a predetermined level of performance in executing the program.