System for and method of operating a programmable column fail counter for redundancy allocation

• US 20020108073A1
• Filed: 02/02/2001
• Published: 08/08/2002
• Est. Priority Date: 02/02/2001
• Status: Abandoned Application

• Current Assignee: Hewlett-Packard Development Company, L.P. (HP Inc.)
• Original Assignee: Hewlett-Packard Development Company, L.P. (HP Inc.)
• Inventors: Hughes, Brian William
• Application Number:
  US09/777,202
• Publication Number:
  US 20020108073A1
• Time in Patent Office: Days
• US Class Current: 714/7
• CPC Class Codes: G11C 29/44 Indication or identification of errors, e.g. for repair
• CPC Class Codes: G11C 29/72 with optimized replacement algorithms

Abstract

The present invention includes a system and a methodology for eliminating faulty memory cells in a memory array with replacement columns of memory cells and replacement rows of memory cells. The individual memory cells are checked to ensure that each is operational. Non-operational cells are replaced by first replacing columns which contain a number of non-operational cells with spare columns and second removing any remaining non-operational cells by replacing the rows containing those non-operational cells with spare rows.

Claims

1. A method of eliminating faulty memory cells from an active part of a memory array, the method comprising the steps of:

determining if cells in each column group of the memory array are defective;

configuring column groups of said memory array to replace ones of said column groups which include more than a predetermined number of defective cells with spare column groups;

identifying by row remaining defective cells not replaced by said step of configuring column groups of said memory array; and

configuring rows of said memory array to replace ones of said rows including said remaining defective cells.

2. The method of claim 1 wherein said step of determining includes the step of testing memory cells of said memory array to identify defective cells and counting a number of said defective cells identified in each of said column groups.

3. The method of claim 2 wherein said step of counting includes setting a threshold and counting said defective cells up to said threshold.

4. The method of claim 1 wherein said step of determining if cells in each column group of the memory array are defective further comprises the steps of:

generating at least one memory address;

writing data to a memory cell at said one memory address;

reading said data from said memory cell at said memory address; and

comparing said data written to said memory cell at said memory address with said data read from said memory cell at said memory address.

5. The method of claim 1 wherein the step of configuring column groups of said memory array includes the step of configuring bit line multiplexers to shift-in a replacement column group of memory cells into said array and the step of configuring rows of said memory array includes the step of translating a row address signal designating said ones of said rows including said remaining defective cells to instead select one or more spare rows of memory cells.

6. The method of claim 1 wherein the step of identifying said remaining defective cells includes the step of testing said memory array after performing said step of configuring said column groups.

7. The method of claim 1 wherein said step of determining is performed by built-in self test.

8. The method of claim 1 wherein said steps of configuring column groups and configuring rows are performed by built-in self repair.

9. A system for eliminating faulty memory cells from a memory array comprising:

a memory cell tester for determining non-operational cells;

a column group reconfigurer for replacing ones of said column groups which contain a predetermined number of non-operational cells;

a remaining non-operational cell identifier which identifies remaining non-operational cells in said memory array; and

a row reconfigurer for replacing ones of said rows which contain non-operational cells.

10. The system of claim 9 wherein said memory cell tester further counts the number of non-operational cells in each of the column groups.

11. The system of claim 10 wherein said memory cell tester includes a threshold and counts the number of non-operational cells up to said threshold.

12. The system of claim 9 wherein said memory cell tester further comprises:

a memory cell test data generator configured to write values in said memory cell;

a memory cell data output configured to read values from said memory cell;

a first register configured to store the value written into said memory cell;

a comparator configured to compare said value stored in said first register with said value read from said memory; and

a second register configured to record a result from said comparator.

13. The system of claim 9 wherein:

said column group reconfigurer includes bit line multiplexers to shift a replacement column of memory cells into said array; and

wherein said row reconfigurer further includes a row address signal which selects one or more spare rows of memory cells.

14. The system of claim 9 further comprising:

a semiconductor substrate; and

a memory array found on a portion of said semiconductor substrate;

where said memory cell tester, column group reconfigurer, remaining cell identifier and row reconfigurer are all formed in common with said memory array on said semiconductor substrate.

15. The system of claim 14 further comprising built-in self test and built-in self repair.

17. The method of claim 16 wherein said step of determining includes a step of testing memory cells of said memory array to determine defective ones of said cells and counting said defective cells in each of the rows.

18. The method of claim 17 wherein said step of counting includes setting a threshold and counting said defective cells up to said threshold.

19. The method of claim 16 wherein said step of determining if cells in each row of the memory array are operational further comprises the steps of:

generating at least one memory address;

writing data to at least one memory cell at said memory address;

reading said data from said memory cell at said memory address; and

comparing said data written to said memory cell at said memory address with said data read from said memory cell at said memory address.

20. The method of claim 16 wherein the step of configuring rows of said memory array includes a step of activating an alternate word line to shift in a replacement row of memory cells into said array.

16. A method of eliminating faulty memory cells from a memory array, the method comprising the steps of:

determining if cells in each row of the memory array are operational;

configuring rows of said memory array to replace ones of said rows which include a predetermined number of non-operational cell with spare rows;

identifying remaining defective cells not replaced by said set of configuring rows of said memory array; and

configuring column groups of said memory array to replace ones of said column groups including said remaining defective cells.