Process for providing seed layers for integrated circuit metallurgy
First Claim
1. A metal layer in an integrated circuit, comprising:
- a number of first level vias connecting to a number of silicon devices in a substrate; and
a number of first level metal lines formed above and connecting to the number of first level vias;
a barrier/adhesion layer having a thickness in the range of 5 to 150 Angstroms formed on the number of first level metal lines; and
a seed layer having a thickness in the range of 5 to 150 Angstroms formed at least between a portion of the barrier/adhesion layer and the number of first level metal lines.
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Accused Products
Abstract
Structures are provided which improve performance in integrated circuits. The structures include a diffusion barrier and a seed layer in an integrated circuit both formed using a low energy ion implantation followed by a selective deposition of metal lines for the integrated circuit. The low energy ion implantation allows for the distinct placement of both the diffusion barrier and the seed layer. Structures are formed with a barrier/adhesion layer deposited in the number of trenches using a low energy ion implantation, e.g. a 100 to 800 electron volt (eV) ion implantation. A seed layer is deposited on the barrier/adhesion layer in the number of trenches also using the low energy ion implantation. Such structures include aluminum, copper, gold, and silver metal interconnects.
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Citations
37 Claims
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1. A metal layer in an integrated circuit, comprising:
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a number of first level vias connecting to a number of silicon devices in a substrate; and
a number of first level metal lines formed above and connecting to the number of first level vias;
a barrier/adhesion layer having a thickness in the range of 5 to 150 Angstroms formed on the number of first level metal lines; and
a seed layer having a thickness in the range of 5 to 150 Angstroms formed at least between a portion of the barrier/adhesion layer and the number of first level metal lines. - View Dependent Claims (2, 3, 4, 5)
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6. An integrated memory circuit, comprising:
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a substrate including one or more transistors;
an insulator layer overlying the substrate having one or more first level vias connecting to the one or more transistors in the substrate; and
a polyimide layer overlying the insulator layer including one or more conductive structures formed above and connecting to the one or more first level vias, each of the one or more conductive structures including;
a number of first level metal lines;
a barrier/adhesion layer having a thickness in the range of 5 to 150 Angstroms formed on the number of first level metal lines; and
a seed layer having a thickness in the range of 5 to 150 Angstroms formed at least between a portion of the barrier/adhesion layer and the number of first level metal lines. - View Dependent Claims (24, 26, 27)
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7. A system, comprising:
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a processor; and
an integrated memory circuit coupled to the processor, wherein the integrated memory circuit further includes;
a substrate including one or more transistors;
an insulator layer overlying the substrate having one or more first level vias connecting to the one or more transistors in the substrate; and
a polyimide layer overlying the insulator layer including one or more conductive structures formed above and connecting to the one or more first level vias, each of the one or more conductive structures including;
a number of first level metal lines;
a barrier/adhesion layer having a thickness in the range of 5 to 150 Angstroms formed on the number of-first level metal lines; and
a seed layer having a thickness in the range of 5 to 150 Angstroms formed at least between a portion of the barrier/adhesion layer and the number of first level metal lines. - View Dependent Claims (8, 9)
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10. A metal layer in an integrated circuit, comprising:
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a number of first level vias in a first insulator layer connecting to a number of silicon devices in a substrate; and
an oxide layer formed over the number of first level vias in the first insulator layer, wherein the oxide layer includes a number of conductive structures connecting from a top surface of the oxide layer to the number of first level vias, each conductive structure, comprising;
a layer of Titanium or Zirconium having a thickness of approximately 50 Angstroms;
a first layer of Aluminum on the layer of Titanium or Zirconium having a thickness of approximately 50 Angstroms;
a layer of Copper on the first layer of Aluminum having a thickness of approximately 10 Angstroms; and
a second layer of Aluminum on the layer of Copper having a thickness of approximately 50 Angstroms. - View Dependent Claims (28, 29)
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11. A metal interconnect in an integrated circuit, comprising:
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a number of first level vias in a first insulator layer connecting to a number of silicon devices in a substrate; and
an oxide layer formed over the number of first level vias in the first insulator layer, wherein the oxide layer includes a number of conductive structures connecting from a top surface of the oxide layer to the number of first level vias, each conductive structure, comprising;
a layer of tantalum having a thickness of approximately 100 Angstroms;
a layer of Nitrogen on the layer of tantalum;
a seed layer of Copper on layer of Nitrogen having a thickness of approximately 100 Angstroms; and
a copper metal line formed on the seed layer of copper. - View Dependent Claims (12, 14, 15, 16, 17, 19, 20, 21, 22, 23, 25)
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13. A wiring structure in an integrated circuit, comprising:
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a number of first level vias in a first insulator layer connecting to a number of silicon devices in a substrate; and
a first number of conductive structures formed over and connecting to the number of first level vias in the first insulator layer, each conductive structure, comprising;
a layer of zirconium having a thickness of approximately 15 Angstroms;
a seed layer of copper on the layer of zirconium having a thickness of approximately 50 Angstroms; and
a copper metal line formed on the seed layer of copper.
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18. A multilayer wiring structure in an integrated circuit assembly, comprising:
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a number of first level vias in a first insulator layer connecting to a number of silicon devices in a substrate;
a first number of conductive structures formed over and connecting to the number of first level vias in the first insulator layer, each conductive structure, comprising;
a first barrier/adhesion layer having a thickness in the range of 5 to 150 Angstroms;
a first seed layer formed on at least a portion of the barrier/adhesion layer having a thickness in the range of 5 to 150 Angstroms; and
a first core conductor formed on the first seed layer and within the first barrier/adhesion layer; and
a second number of conductive structures includes a number of second level vias and a number of second level metal lines, wherein the second number of conductive structures are formed over and connect to the first number of conductive structures, and wherein each of the second number of conductive structures includes;
a second barrier/adhesion layer having a thickness in the range of 5 to 150 Angstroms;
a second seed layer formed on at least a portion of the barrier/adhesion layer having a thickness in the range of 5 to 150 Angstroms; and
a second core conductor formed on the second seed layer and within the second barrier/adhesion layer.
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30. An integrated circuit, comprising:
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a substrate including one or more transistors;
an insulator layer overlying the substrate having one or more first level vias connecting to the one or more transistors in the substrate; and
a polyimide layer overlying the insulator layer including one or more conductive structures formed above and connecting to the one or more first level vias, each of the one or more conductive structures including;
a number of first level metal lines;
a barrier/adhesion layer having a thickness in the range of 5 to 150 Angstroms formed on the number of first level metal lines; and
a seed layer having a thickness in the range of 5 to 150 Angstroms formed at least between a portion of the barrier/adhesion layer and the number of first level metal lines. - View Dependent Claims (31, 32, 33, 34, 36, 37)
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35. An integrated circuit, comprising:
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a substrate including one or more transistors;
an insulator layer overlying the substrate having one or more first level vias connecting to the one or more transistors in the substrate; and
an oxide layer overlying the insulator layer including one or more conductive structures formed above and connecting to the one or more first level vias, each of the one or more conductive structures including;
a layer of Titanium or Zirconium having a thickness of approximately 50 Angstroms;
a first layer of Aluminum on the layer of Titanium or Zirconium having a thickness of approximately 50 Angstroms;
a layer of Copper on the first layer of Aluminum having a thickness of approximately 10 Angstroms; and
a second layer of Aluminum on the layer of Copper having a thickness of approximately 50 Angstroms.
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Specification