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Process for providing seed layers for integrated circuit metallurgy

  • US 20020109233A1
  • Filed: 04/05/2002
  • Published: 08/15/2002
  • Est. Priority Date: 01/18/2000
  • Status: Active Grant
First Claim
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1. A metal layer in an integrated circuit, comprising:

  • a number of first level vias connecting to a number of silicon devices in a substrate; and

    a number of first level metal lines formed above and connecting to the number of first level vias;

    a barrier/adhesion layer having a thickness in the range of 5 to 150 Angstroms formed on the number of first level metal lines; and

    a seed layer having a thickness in the range of 5 to 150 Angstroms formed at least between a portion of the barrier/adhesion layer and the number of first level metal lines.

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