Process for providing seed layers for integrated circuit metallurgy

• US 20020109233A1
• Filed: 04/05/2002
• Published: 08/15/2002
• Est. Priority Date: 01/18/2000
• Status: Active Grant

• Current Assignee: Micron Technology, Inc.
• Original Assignee: Micron Technology, Inc.
• Inventors: Farrar, Paul A.
• Granted Patent: US 7,105,914 B2
• Time in Patent Office: Days
• US Class Current: 257/762
• CPC Class Codes: H01L 21/76843 formed in openings in a dielectric
• CPC Class Codes: H01L 21/76846 Layer combinations
• CPC Class Codes: H01L 21/76849 the layer being positioned on top of the main fill metal
• CPC Class Codes: H01L 21/76859 by ion implantation
• CPC Class Codes: H01L 21/76867 characterized by methods of formation other than PVD, CVD or deposition from a liquids PVD H01L21/2855; CVD H01L21/28556; deposition from liquids H01L21/288
• CPC Class Codes: H01L 21/76874 for electroless plating
• CPC Class Codes: H01L 21/76885 By forming conductive members before deposition of protective insulating material, e.g. pillars, studs
• CPC Class Codes: H01L 2221/1089 Stacks of seed layers

Abstract

Structures are provided which improve performance in integrated circuits. The structures include a diffusion barrier and a seed layer in an integrated circuit both formed using a low energy ion implantation followed by a selective deposition of metal lines for the integrated circuit. The low energy ion implantation allows for the distinct placement of both the diffusion barrier and the seed layer. Structures are formed with a barrier/adhesion layer deposited in the number of trenches using a low energy ion implantation, e.g. a 100 to 800 electron volt (eV) ion implantation. A seed layer is deposited on the barrier/adhesion layer in the number of trenches also using the low energy ion implantation. Such structures include aluminum, copper, gold, and silver metal interconnects.

Claims

1. A metal layer in an integrated circuit, comprising:

a number of first level vias connecting to a number of silicon devices in a substrate; and

a number of first level metal lines formed above and connecting to the number of first level vias;

a barrier/adhesion layer having a thickness in the range of 5 to 150 Angstroms formed on the number of first level metal lines; and

a seed layer having a thickness in the range of 5 to 150 Angstroms formed at least between a portion of the barrier/adhesion layer and the number of first level metal lines.

2. The metal layer of claim 1, wherein the barrier/adhesion layer having a thickness in the range of 5 to 150 Angstroms includes a barrier/adhesion layer selected from the group consisting of titanium, zirconium, and hafnium.

3. The metal layer of claim 1, wherein the number of first level vias connecting to a number of silicon devices in a substrate are surrounded by an insulator layer.

4. The metal layer of claim 1, wherein the barrier/adhesion layer formed on the number of first level metal lines is surrounded by a polyimide insulator layer.

5. The metal layer of claim 1, wherein the number of first level metal lines includes a number of first level metal lines is selected from the group consisting of Aluminum, Copper, Silver, and Gold.

6. An integrated memory circuit, comprising:

a substrate including one or more transistors;

an insulator layer overlying the substrate having one or more first level vias connecting to the one or more transistors in the substrate; and

a polyimide layer overlying the insulator layer including one or more conductive structures formed above and connecting to the one or more first level vias, each of the one or more conductive structures including;

a number of first level metal lines;

a barrier/adhesion layer having a thickness in the range of 5 to 150 Angstroms formed on the number of first level metal lines; and

a seed layer having a thickness in the range of 5 to 150 Angstroms formed at least between a portion of the barrier/adhesion layer and the number of first level metal lines.

24. The integrated memory circuit of claim 6, wherein the insulator layer includes Si₃N₄.

26. The integrated memory circuit of claim 6, wherein the barrier/adhesion layer having a thickness in the range of 5 to 150 Angstroms includes a barrier/adhesion layer selected from the group consisting of titanium, zirconium, and hafnium.

27. The integrated memory circuit of claim 6, wherein the seed layer having a thickness in the range of 5 to 150 Angstroms formed at least between a portion of the barrier/adhesion layer and the number of first level metal lines includes a copper seed layer, and the number of first level metal lines includes a number of copper metal lines.

7. A system, comprising:

a processor; and

an integrated memory circuit coupled to the processor, wherein the integrated memory circuit further includes;

a substrate including one or more transistors;

an insulator layer overlying the substrate having one or more first level vias connecting to the one or more transistors in the substrate; and

a polyimide layer overlying the insulator layer including one or more conductive structures formed above and connecting to the one or more first level vias, each of the one or more conductive structures including;

a number of first level metal lines;

a barrier/adhesion layer having a thickness in the range of 5 to 150 Angstroms formed on the number of-first level metal lines; and

a seed layer having a thickness in the range of 5 to 150 Angstroms formed at least between a portion of the barrier/adhesion layer and the number of first level metal lines.

8. The system of claim 7, wherein the barrier/adhesion layer having a thickness in the range of 5 to 150 Angstroms includes a barrier/adhesion layer selected from the group consisting of titanium, zirconium, and hafnium.

9. The system of claim 7, wherein the a seed layer having a thickness in the range of 5 to 150 Angstroms formed at least between a portion of the barrier/adhesion layer and the number of first level metal lines includes a copper seed layer, and the number of first level metal lines includes a number of copper metal lines.

10. A metal layer in an integrated circuit, comprising:

a number of first level vias in a first insulator layer connecting to a number of silicon devices in a substrate; and

an oxide layer formed over the number of first level vias in the first insulator layer, wherein the oxide layer includes a number of conductive structures connecting from a top surface of the oxide layer to the number of first level vias, each conductive structure, comprising;

a layer of Titanium or Zirconium having a thickness of approximately 50 Angstroms;

a first layer of Aluminum on the layer of Titanium or Zirconium having a thickness of approximately 50 Angstroms;

a layer of Copper on the first layer of Aluminum having a thickness of approximately 10 Angstroms; and

a second layer of Aluminum on the layer of Copper having a thickness of approximately 50 Angstroms.

28. The metal layer of claim 10, wherein the insulator layer includes Si₃N₄ having a thickness between about 100 Å

to about 500 Å

.

29. The metal layer of claim 10, wherein the oxide layer includes a fluorinated silicon oxide layer.

11. A metal interconnect in an integrated circuit, comprising:

a number of first level vias in a first insulator layer connecting to a number of silicon devices in a substrate; and

an oxide layer formed over the number of first level vias in the first insulator layer, wherein the oxide layer includes a number of conductive structures connecting from a top surface of the oxide layer to the number of first level vias, each conductive structure, comprising;

a layer of tantalum having a thickness of approximately 100 Angstroms;

a layer of Nitrogen on the layer of tantalum;

a seed layer of Copper on layer of Nitrogen having a thickness of approximately 100 Angstroms; and

a copper metal line formed on the seed layer of copper.

12. The metal layer of claim 11, wherein each conductive structure further includes a layer of tantalum nitride forming a top surface of each conductive structure such that the top surface of each conductive structure is level with the top surface of the oxide layer.

14. The wiring structure of claim 13, wherein each conductive structure further includes a layer of aluminum having a thickness of approximately 50 Angstroms formed between the seed layer of copper and the copper metal line.

15. The wiring structure of claim 13, wherein the wiring structure further includes a polymer layer surrounding the number of conductive structures.

16. The wiring structure of claim 15, wherein the polymer layer includes a foamed polymer layer.

17. The wiring structure of claim 13, wherein the wiring structure further includes:

a second number of conductive structures including a number of second level vias and a number of second level metal lines formed above and connecting to the first number of conductive structures, wherein each of the second number of conductive structures includes;

a layer of zirconium having a thickness of approximately 15 Angstroms;

a seed layer of copper on at least a portion of the layer of zirconium having a thickness of approximately 50 Angstroms; and

a core copper conductor over the seed layer and within the layer of zirconium.

19. The multilayer wiring structure of claim 18, wherein the first and the second number of conductors are surrounded by a polyimide layer.

20. The multilayer wiring structure of claim 18, wherein the polyimide layer includes a foamed polyimide layer.

21. The multilayer wiring structure of claim 18, wherein the first and the second barrier/adhesion layers include a first and a second barrier/adhesion layer selected from the group consisting of tantalum nitride, titanium, zirconium, and hafnium.

22. The multilayer wiring structure of claim 18, wherein the first and the second core conductors include a metal conductor selected from the group consisting of Aluminum, Copper, Silver, and Gold.

23. The multilayer wiring structure of claim 18, wherein the first and the second seed layers include a first and a second seed layer selected from the group consisting of Aluminum, Copper, Silver, and Gold.

25. The integrated memory circuit of claim 24, wherein the Si₃N₄ has a thickness between about 100 Å

to about 500 Å

.

13. A wiring structure in an integrated circuit, comprising:

a number of first level vias in a first insulator layer connecting to a number of silicon devices in a substrate; and

a first number of conductive structures formed over and connecting to the number of first level vias in the first insulator layer, each conductive structure, comprising;

a layer of zirconium having a thickness of approximately 15 Angstroms;

a seed layer of copper on the layer of zirconium having a thickness of approximately 50 Angstroms; and

a copper metal line formed on the seed layer of copper.

18. A multilayer wiring structure in an integrated circuit assembly, comprising:

a number of first level vias in a first insulator layer connecting to a number of silicon devices in a substrate;

a first number of conductive structures formed over and connecting to the number of first level vias in the first insulator layer, each conductive structure, comprising;

a first barrier/adhesion layer having a thickness in the range of 5 to 150 Angstroms;

a first seed layer formed on at least a portion of the barrier/adhesion layer having a thickness in the range of 5 to 150 Angstroms; and

a first core conductor formed on the first seed layer and within the first barrier/adhesion layer; and

a second number of conductive structures includes a number of second level vias and a number of second level metal lines, wherein the second number of conductive structures are formed over and connect to the first number of conductive structures, and wherein each of the second number of conductive structures includes;

a second barrier/adhesion layer having a thickness in the range of 5 to 150 Angstroms;

a second seed layer formed on at least a portion of the barrier/adhesion layer having a thickness in the range of 5 to 150 Angstroms; and

a second core conductor formed on the second seed layer and within the second barrier/adhesion layer.

30. An integrated circuit, comprising:

a substrate including one or more transistors;

an insulator layer overlying the substrate having one or more first level vias connecting to the one or more transistors in the substrate; and

a polyimide layer overlying the insulator layer including one or more conductive structures formed above and connecting to the one or more first level vias, each of the one or more conductive structures including;

a number of first level metal lines;

a barrier/adhesion layer having a thickness in the range of 5 to 150 Angstroms formed on the number of first level metal lines; and

a seed layer having a thickness in the range of 5 to 150 Angstroms formed at least between a portion of the barrier/adhesion layer and the number of first level metal lines.

31. The integrated circuit of claim 30, wherein the insulator layer includes Si₃N₄.

32. The integrated circuit of claim 31, wherein the Si₃N₄ has a thickness between about 100 Å

to about 500 Å

.

33. The integrated circuit of claim 30, wherein the barrier/adhesion layer having a thickness in the range of 5 to 150 Angstroms includes a barrier/adhesion layer selected from the group consisting of titanium, zirconium, and hafnium.

34. The integrated circuit of claim 30, wherein the seed layer having a thickness in the range of 5 to 150 Angstroms formed at least between a portion of the barrier/adhesion layer and the number of first level metal lines includes a copper seed layer, and the number of first level metal lines includes a number of copper metal lines.

36. The integrated circuit of claim 35, wherein the insulator layer includes Si₃N₄ having a thickness between about 100 Å

to about 500 Å

.

37. The integrated circuit of claim 35, wherein the oxide layer includes a fluorinated silicon oxide layer.

35. An integrated circuit, comprising:

a substrate including one or more transistors;

an insulator layer overlying the substrate having one or more first level vias connecting to the one or more transistors in the substrate; and

an oxide layer overlying the insulator layer including one or more conductive structures formed above and connecting to the one or more first level vias, each of the one or more conductive structures including;

a layer of Titanium or Zirconium having a thickness of approximately 50 Angstroms;

a first layer of Aluminum on the layer of Titanium or Zirconium having a thickness of approximately 50 Angstroms;

a layer of Copper on the first layer of Aluminum having a thickness of approximately 10 Angstroms; and

a second layer of Aluminum on the layer of Copper having a thickness of approximately 50 Angstroms.