Organic electroluminescent display control system

• US 20020109651A1
• Filed: 12/14/2001
• Published: 08/15/2002
• Est. Priority Date: 01/02/2001
• Status: Active Grant

• Current Assignee: Samsung Display Company Limited (Samsung Electronics Co. Ltd.)
• Original Assignee: Samsung SDI Company Limited
• Inventors: Oh, Choon Yul
• Granted Patent: US 6,850,231 B2
• Time in Patent Office: Days
• US Class Current: 345/76
• CPC Class Codes: G09G 2340/0492 Change of orientation of the displayed image, e.g. upside-down, mirrored
• CPC Class Codes: G09G 3/3208 organic, e.g. using organic light-emitting diodes [OLED]
• CPC Class Codes: G09G 5/393 Arrangements for updating the contents of the bit-mapped memory
• CPC Class Codes: G09G 5/395 Arrangements specially adapted for transferring the contents of the bit-mapped memory to the screen G09G5/399 takes precedence

Abstract

An organic electroluminescent EL display control system includes a display panel having a common terminal arranged on a lower portion thereof and a segment terminal arranged on a side portion thereof, and a driver controller having the driver controller including a display RAM storing data, the data being vertically read from the display RAM.

Claims

1. An organic EL display control system comprising:

a display panel including data lines and scan lines, the data lines arranged in a transverse direction, the scan lines arranged in a perpendicular direction to the data lines;

a driver controller having a display RAM storing data,

wherein the data is vertically read from the display RAM and transmitted to the display panel.

2. The system of claim 1, wherein the driver controller further comprises:

a common driver circuit connected to the scan lines of the display panel;

a segment driver circuit connected to the data lines of the display panel,

a page address generating circuit connected to the display RAM through address buses and designating vertically a page address to store the data during a write operation;

a data latch circuit connected to the display RAM through data buses so that the data of a column may be output from the display RAM at a time during a read operation;

a line address generating circuit connected to the display RAM through address buses and designating the column to be displayed during a read operation;

a column address generating circuit connected to the display RAM through address buses and designating a column address during a write operation; and

a controller controlling each of the common driver circuit, the segment driver circuit, the page address generating circuit, the data latch circuit, the line address generating circuit, and the column address generating circuit.

3. The system of claim 1, wherein a line length between the common driver circuit and the scan lines is shorter than that between the segment driver circuit and the data lines.

4. The system of claim 1, wherein the data is an image, and the image is turned up by conversely changing a connection order of pins of an input side of the display RAM.

5. The system of claim 1, wherein the data is an image, and the image is turned up by conversely changing a connection order of pins of an input side of the display RAM.

6. The system of claim 2, wherein a line length between the common driver circuit and the scan lines is shorter than that between the segment driver circuit and the data lines.

7. An organic EL display control system, comprising:

a display panel including a segment terminal and a common terminal, the segment terminal connected to data lines, the common terminal connected to scan lines arranged in a perpendicular direction to the data lines;

a driver controller having a display RAM storing data and outputting the data from the display RAM in the same direction as a longitudinal direction of the scan lines.

8. The system of claim 7, wherein the data lines are arranged in a transverse direction, and the scan lines are arranged in a vertical direction.

9. The system of claim 8, wherein a line length between the common terminal and the driver controller is shorter than that between the segment terminal and the driver controller.

10. The system of claim 7, wherein the driver controller comprises:

a common driver circuit connected to the common terminal of the display panel;

a segment driver circuit connected to the segment terminal of the display panel;

a page address generating circuit connected to the display RAM through address buses and designating vertically a page address to store the data during a write operation;

a data latch circuit connected to the display RAM through data buses so that the data of a column may be output from the display RAM at a time during a read operation;

a line address generating circuit connected to the display RAM through address buses and designating the column to be displayed during a read operation;

a column address generating circuit connected to the display RAM through address buses and designating a column address during a write operation; and

a controller controlling each of the common driver circuit, the segment driver circuit, the page address generating circuit, the data latch circuit, the line address generating circuit, and the column address generating circuit.

11. The system of claim 7, wherein the data is an image, and the image is turned up by conversely changing a connection order of pins of an output side of the display RAM.

12. The system of claim 10, wherein a line length between the common driver circuit and the common terminal is shorter than that between the segment driver circuit and the segment terminal.