Checkerboard buffer

• US 20020110351A1
• Filed: 07/17/2001
• Published: 08/15/2002
• Est. Priority Date: 02/15/2001
• Status: Active Grant

• Current Assignee: Sony Corporation (Sony Group Corp.), Sony Electronics Inc. (Sony Group Corp.)
• Original Assignee: Sony Corporation (Sony Group Corp.), Sony Electronics Inc. (Sony Group Corp.)
• Inventors: Champion, Mark, Dockter, Brian
• Granted Patent: US 6,831,651 B2
• Time in Patent Office: Days
• US Class Current: 386/40
• CPC Class Codes: G06T 1/60 Memory management
• CPC Class Codes: G09G 2352/00 Parallel handling of streams of display data
• CPC Class Codes: G09G 2360/123 using interleaving
• CPC Class Codes: G09G 2360/128 Frame memory using a Synchronous Dynamic RAM [SDRAM]
• CPC Class Codes: G09G 5/39 Control of the bit-mapped memory
• CPC Class Codes: G09G 5/399 using two or more bit-mapped memories, the operations of which are switched in time, e.g. ping-pong buffers
• CPC Class Codes: G11C 7/1042 using interleaving techniques, i.e. read-write of one part of the memory while preparing another part
• CPC Class Codes: H04N 21/44004 involving video buffer management, e.g. video decoder buffer or video display buffer
• CPC Class Codes: H04N 5/14 Picture signal circuitry for video frequency region cameras or camera modules comprising electronic image sensors, or control thereof H04N23/00
• CPC Class Codes: H04N 5/46 for receiving on more than one standard at will deflecting circuits of multi-standard receivers H04N3/27
• CPC Class Codes: H04N 5/7416 involving the use of a spatial light modulator, e.g. a light valve, controlled by a video signal
• CPC Class Codes: H04N 7/01 Conversion of standards , e.g. involving analogue television standards or digital television standards processed at pixel level
• CPC Class Codes: H04N 7/012 Conversion between an interlaced and a progressive signal for graphics images G09G2310/0229
• CPC Class Codes: H04N 7/0132 the field or frame frequency of the incoming video signal being multiplied by a positive integer, e.g. for flicker reduction

Abstract

Methods and apparatus for storing and retrieving data in parallel but in different orders. In one implementation, data for pixels is stored according to a checkerboard pattern, alternately between two memory devices, forming a checkerboard buffer. In one implementation, a checkerboard buffer includes: a data source, providing data in a first order; a data destination, receiving data in a second order; at least two memory devices, each memory device having a plurality of memory locations, where data is stored in parallel to the memory devices and retrieved in parallel from the memory devices; a first data switch connected to the data source and each of the memory devices, where the first data switch controls which data is stored to which memory device; and a second data switch connected to the data destination and each of the memory devices, where the second data switch controls providing data to the data destination according to the second order.

Claims

1. A checkerboard buffer, comprising:

a data source, providing data in a first order;

a data destination, receiving data in a second order;

at least two memory devices, each memory device having a plurality of memory locations, where data is stored in parallel to the memory devices and retrieved in parallel from the memory devices;

a first data switch connected to the data source and each of the memory devices, where the first data switch controls which data is stored to which memory device; and

a second data switch connected to the data destination and each of the memory devices, where the second data switch controls providing data to the data destination according to the second order.

2. The checkerboard buffer of claim 1, where:

the checkerboard buffer is a frame buffer for storing a frame of pixels, the frame having horizontal rows of pixels and vertical columns of pixels;

the pixels are numbered from left to right, top to bottom, starting from 0 in the upper left corner;

the rows are numbered from top to bottom, starting from 0 at the top; and

the columns are numbered from left to right, starting from 0 at the left.

3. The checkerboard buffer of claim 2, where:

the data is pixel data;

each pixel in the frame has corresponding pixel data;

pixel data for each pixel is stored in a respective memory location in a memory device; and

pixel data stored in parallel is stored at the same address in each memory device.

4. The checkerboard buffer of claim 3, where the pixel data is provided according to a high definition screen resolution of 1920 columns of pixels and 1080 rows of pixels per frame.

5. The checkerboard buffer of claim 4, where data is provided by the data source at a rate of 600 megabytes per second.

6. The checkerboard buffer of claim 4, where data is received by the data destination at a rate of 600 megabytes per second.

7. The checkerboard buffer of claim 4, where the data source provides pixel data according to a progressive signal.

8. The checkerboard buffer of claim 3, where each pixel has 32 bits of pixel data.

9. The checkerboard buffer of claim 3, where pixel data for two pixels is stored in parallel in one clock cycle, pixel data for one pixel to one memory device and pixel data for the other pixel to another memory device.

10. The checkerboard buffer of claim 3, where pixel data for two pixels is retrieved in parallel in one clock cycle, pixel data for one pixel from one memory device and pixel data for the other pixel from another memory device.

11. The checkerboard buffer of claim 3, where pixel data is stored according to horizontal rows of pixels in the frame.

12. The checkerboard buffer of claim 11, where which memory stores pixel data for which pixel switches with each horizontal row.

13. The checkerboard buffer of claim 3, where:

pixel data for even-numbered pixels in even-numbered rows is stored in a first memory device;

pixel data for odd-numbered pixels in even-numbered rows is stored in a second memory device;

pixel data for even-numbered pixels in odd-numbered rows is stored in the second memory device; and

pixel data for odd-numbered pixels in odd-numbered rows is stored in the first memory device.

14. The checkerboard buffer of claim 3, where pixel data is stored according to horizontal pixel pairs.

15. The checkerboard buffer of claim 14, where the pixel data for each pixel of a horizontal pixel pair is stored at the same address in each of two memory devices.

16. The checkerboard buffer of claim 3, where pixel data is retrieved according to vertical columns of pixels in the frame.

17. The checkerboard buffer of claim 16, where the order that pixel data from two memory devices is provided to the data destination switches with each vertical column.

18. The checkerboard buffer of claim 3, where pixel data is retrieved according to vertical pixel pairs.

19. The checkerboard buffer of claim 18, where the pixel data for each pixel of a vertical pixel pair is stored at a different address in each of two memory devices.

20. The checkerboard buffer of claim 3, where the first data switch switches which memory device to store pixel data for two pixels with each horizontal row of pixels.

21. The checkerboard buffer of claim 20, where the first data switch switches based on an address of a memory location to store the pixel data.

22. The checkerboard buffer of claim 20, where the first data switch switches based on a counter reaching a multiple of the number of pixels in a horizontal row.

23. The checkerboard buffer of claim 20, where the first data switch switches based on a horizontal synchronization signal.

24. The checkerboard buffer of claim 20, where the first data switch switches in response to a flip-flop being toggled.

25. The checkerboard buffer of claim 3, where the second data switch switches the order pixel data from each of two memory devices is provided to the data destination with each vertical column of pixels.

26. The checkerboard buffer of claim 25, where the second data switch switches based on an address of a memory location from which to retrieve pixel data.

27. The checkerboard buffer of claim 25, where the second data switch switches based on a counter reaching a maximum row value, indicating the last row in a column.

28. The checkerboard buffer of claim 27, where the maximum row value is 1080.

29. The checkerboard buffer of claim 25, where the second data switch switches in response to a flip-flop being toggled.

30. The checkerboard buffer of claim 3, where addresses of memory locations are generated using one or more counters.

31. The checkerboard buffer of claim 30, where the data source generates addresses for storing pixel data.

32. The checkerboard buffer of claim 30, where the data destination generates addresses for retrieving pixel data.

33. The checkerboard buffer of claim 30, where the counters include a row counter and a column counter.

34. The checkerboard buffer of claim 33, where the row counter and the column counter indicate an address stored in a look-up table.

35. The checkerboard buffer of claim 33, where addresses are mathematically derived from the values of the row counter and the column counter.

36. The checkerboard buffer of claim 30, where one counter counts pixel pairs.

37. The checkerboard buffer of claim 3, where pixel data is retrieved at twice or more than the rate pixel data is stored.

38. The checkerboard buffer of claim 37, where pixel data is stored at a rate supporting 60 frames per second, and pixel data is retrieved at a rate supporting 120 frames per second.

39. The checkerboard buffer of claim 37, where pixel data is retrieved for 64 pixels for every 32 pixels of pixel data that is stored.

40. The checkerboard buffer of claim 2, where the data destination is a grating light valve system including one or more grating light valves.

41. The checkerboard buffer of claim 40, where the frame is a high definition screen resolution frame having 1920 columns of pixels and 1080 rows of pixels per frame.

42. The checkerboard buffer of claim 40, where the grating light valve system includes three grating light valves, one for each of red, blue, and green.

43. The checkerboard buffer of claim 40, where each grating light valve sweeps one column at a time from left to right and from right to left in alternation.

44. The checkerboard buffer of claim 43, where a counter is used to generate addresses, and further where the counter increments as each grating light valve sweeps from left to right and the counter decrements as each grating light valve sweeps from right to left.

45. The checkerboard buffer of claim 2, where the data destination is a video card.

46. The checkerboard buffer of claim 1, where each memory device is an eight megabyte device.

47. The checkerboard buffer of claim 46, where each memory device is an SDRAM.

48. The checkerboard buffer of claim 46, where each memory device operates at approximately 150 MHZ.

49. The checkerboard buffer of claim 1, further comprising a memory controller that generates addresses for storing and retrieving pixel data.

50. The checkerboard buffer of claim 1, further comprising a memory controller that includes the first data switch and the second data switch, and controls providing pixel data to the memory devices and receiving pixel data from the memory devices.

51. The checkerboard buffer of claim 1, where each memory device is divided into two memory sections, a first memory section for storing data and a second memory section for retrieving data.

52. The checkerboard buffer of claim 51, where a block of data is stored to the first memory sections of the memory devices and a block of data is retrieved from the second memory sections in alternation, and the memory sections switch roles between storing and retrieving.

53. The checkerboard buffer of claim 52, where a block of data is pixel data for a block of 32 pixels.

54. The checkerboard buffer of claim 51, where a counter is used for addressing, and where the counter is alternately reset to the beginning of the first sections or to the beginning of the second sections.

55. A checkerboard buffer system, comprising:

a data source, providing data in a first order;

a data destination, receiving data in a second order;

a checkerboard buffer, storing data from the data source in the first order and providing data to the data destination in the second order.

56. The checkerboard buffer system of claim 55, where the data destination is a video display system.

57. The checkerboard buffer system of claim 56, where the video display system is a grating light valve system including one or more grating light valves.

58. The checkerboard buffer system of claim 55, where the data source is a video source.

59. The checkerboard buffer system of claim 58, where the video source provides pixel data according to a high definition screen resolution having 1920 columns of pixels and 1080 rows of pixels per frame.

60. The checkerboard buffer system of claim 55, where the data is pixel data, and the data source provides pixel data according to horizontal rows of pixels and the data destination receives pixel data according to vertical columns of pixels.

61. A checkerboard buffer, comprising:

a video source providing pixel data for pixels in a frame;

a video destination;

a first memory;

a second memory;

a first data bus connected to the first memory;

a second data bus connected to the second memory;

a first address multiplexor connected to the first memory;

a second address multiplexor connected to the second memory;

a source address bus connected to the video source, the first address multiplexor, and the second address multiplexor;

a first destination address bus connected to the video destination and the first address multiplexor;

a second destination address bus connected to the video destination and the second address multiplexor;

a first data switch connected to the first data bus, the second data bus, and the video source, where the first data switch is between the video source and the first memory and between the video source and the second memory, and where the first data switch switches which memory to store pixel data for two pixels with each horizontal row of pixels; and

a second data switch connected to the first data bus, the second data bus, and the video destination, where the second data switch is between the video destination and the first memory and between the video destination and the second memory, and where the second data switch switches the order pixel data from each of the first memory and the second memory is provided to the video destination with each vertical column of pixels.

62. The checkerboard buffer of claim 61, where the video source generates source addresses for storing pixel data in the first memory and the second memory.

63. The checkerboard buffer of claim 62, where the video source uses a counter to generate source addresses.

64. The checkerboard buffer of claim 61, where the video destination generates a first destination address and a second destination address for storing pixel data in the first memory and the second memory, respectively.

65. The checkerboard buffer of claim 64, where the video destination uses a row counter and a column counter to generate the first destination address and the second destination address.

66. The checkerboard buffer of claim 61, where the first data switch switches based on a horizontal synchronization signal.

67. The checkerboard buffer of claim 61, where the first data switch switches based on an address used to store pixel data.

68. The checkerboard buffer of claim 61, where the second data switch switches based on an address used to retrieve pixel data.

69. The checkerboard buffer of claim 61, where:

each memory is divided into two memory sections, a first memory section for storing data and a second memory section for retrieving data;

a block of data is stored to the first memory sections of the memory devices and a block of data is retrieved from the second memory sections in alternation; and

the memory sections switch roles between storing and retrieving with each frame of pixel data.

70. A checkerboard buffer, comprising:

a video source providing pixel data for pixels in a frame;

a video destination;

a first memory;

a second memory;

a memory controller connected to the first memory and the second memory;

a first data bus connected to the memory controller;

a second data bus connected to the memory controller;

a source address line connected to the video source and the memory controller;

a destination address line connected to the video destination and the memory controller;

a first data switch connected to the first data bus, the second data bus, and the video source, where the first data switch is between the video source and the first memory and between the video source and the second memory, and where the first data switch switches which memory to store pixel data for two pixels with each horizontal row of pixels; and

a second data switch connected to the first data bus, the second data bus, and the video destination, where the second data switch is between the video destination and the first memory and between the video destination and the second memory, and where the second data switch switches the order pixel data from each of the first memory and the second memory is provided to the video destination with each vertical column of pixels.

71. The checkerboard buffer of claim 70, where the memory controller generates addresses for storing and retrieving pixel data.

72. A checkerboard buffer, comprising:

a video source providing pixel data for pixels in a frame;

a video destination;

a first memory;

a second memory;

a memory controller connected to the video source, the video destination, the first memory, and the second memory, where the memory controller switches which memory to store pixel data for two pixels with each horizontal row of pixels and switches the order pixel data from each of the first memory and the second memory is provided to the video destination with each vertical column of pixels;

a source address line connected to the video source and the memory controller; and

a destination address line connected to the video destination and the memory controller.

73. The checkerboard buffer of claim 72, where the memory controller generates addresses for storing and retrieving pixel data.

74. A method of storing pixel data in a checkerboard buffer, comprising:

storing pixel data for a first pair of pixels at a first memory address in a first memory device and a second memory device respectively, where the first pair of pixels are the first two pixels in a first horizontal row of pixels in a frame; and

storing pixel data for a second pair of pixels at a second memory address in the second memory device and the first memory device respectively, where the second pair of pixels are the first two pixels in a second horizontal row of pixels in a frame and are vertically adjacent to the first pair of pixels.

75. The method of claim 74, further comprising:

providing pixel data for a first pixel and a second pixel from a video source to a data switch;

providing a source address to the first memory device and the second memory device, where the source address is a memory address;

controlling a state of the data switch, where in a first state the data switch provides pixel data for the first pixel to the first memory device and pixel data for the second pixel to the second memory device, and in a second state the data switch provides pixel data for the first pixel to the second memory device and pixel data for the second pixel to the first memory device, and where the state switches after storing pixel data for each horizontal row of pixels;

providing the pixel data from the data switch to the first memory device and the second memory device according to the state of the data switch; and

storing the pixel data in the first memory device and the second memory device at the source address.

76. A method of storing pixel data in a checkerboard buffer, comprising:

storing pixel data of a first pixel of a first horizontal row of pixels at a first memory location in a first memory, where the first horizontal row of pixels includes a number of pixels, and where each memory location in the first memory has a corresponding memory address and includes space to store all the pixel data for a pixel;

storing pixel data of a second pixel of the first horizontal row of pixels at a first memory location in a second memory, where each memory location in the second memory has a corresponding memory address and includes space to store all the pixel data for a pixel, where the second pixel of the first horizontal row of pixels is horizontally adjacent to the first pixel of the first horizontal row of pixels, and where the first memory location in the first memory and the first memory location in the second memory have the same memory address;

storing pixel data of a first pixel of a second horizontal row of pixels at a second memory location in the second memory, where the second horizontal row of pixels includes a number of pixels equal in number to the number of pixels in the first horizontal row of pixels, where the first pixel of the second horizontal row of pixels is vertically adjacent to the first pixel of the first horizontal row of pixels, and where the second memory location in the second memory is sequentially separated from the first memory location in the second memory by at least a number of locations equal to one less than one half of the number of pixels in the first horizontal row of pixels; and

storing pixel data of a second pixel of the second horizontal row of pixels at a second memory location in a first memory, where the second pixel of the second horizontal row of pixels is horizontally adjacent to the first pixel of the second horizontal row of pixels and the second pixel of the second horizontal row of pixels is vertically adjacent to the second pixel of the first horizontal row of pixels, where the second memory location in the first memory is sequentially separated from the first memory location in the first memory by at least a number of locations equal to one less than one half of the number of pixels in the first horizontal row of pixels, and where the second memory location in the first memory and the second memory location in the second memory have the same memory address.

77. A method of storing pixel data in a checkerboard buffer, comprising:

storing pixel data for even-numbered pixels in even-numbered horizontal rows of pixels in a first memory, where the first horizontal row of pixels is numbered 0, the first pixel in the first horizontal row of pixels is numbered 0, and each horizontal row of pixels and each pixel are numbered sequentially, incrementing by one;

storing pixel data for odd-numbered pixels in even-numbered horizontal rows of pixels in a second memory;

storing pixel data for even-numbered pixels in odd-numbered horizontal rows of pixels in the second memory; and

storing pixel data for odd-numbered pixels in odd-numbered horizontal rows of pixels in the first memory.

80. The method of claim 79, further comprising:

generating a first destination address and a second destination address, where each destination address is a memory address;

providing the first destination address to the first memory device;

providing the second destination address to the second memory device;

controlling a state of a data switch, where in a first state the data switch provides pixel data from the first memory device to a first input of a data destination and pixel data from the second memory device to a second input of the data destination, and in a second state the data switch provides pixel data from the second memory device to the first input of the data destination and pixel data from the first memory device to the second input of the data destination, and where the state switches after retrieving pixel data for each vertical column of pixels;

providing pixel data from the first memory device stored at the first destination address to the data switch;

providing pixel data from the second memory device stored at the second destination address to the data switch; and

providing pixel data from the data switch to the data destination according to the state of the data switch.

78. A method of storing pixel data in a checkerboard buffer, comprising:

receiving pixel data for each of the pixels in a frame of a screen;

storing pixel data for a first half of the pixels in the frame in a first memory, where none of the pixels for which pixel data is stored in the first memory are horizontally or vertically adjacent to one another in the frame; and

storing pixel data for a second half of the pixels in the frame in a second memory, where none of the pixels for which pixel data is stored in the second memory are horizontally or vertically adjacent to one another in the frame.

79. A method of retrieving pixel data in a checkerboard buffer, comprising:

retrieving pixel data for a first pair of pixels from a first memory address in a first memory device and from a second memory address in a second memory device respectively, where the first pair of pixels are the first two pixels in a first vertical column of pixels in a frame; and

retrieving pixel data for a second pair of pixels from the first memory address in the second memory device and from the second memory address in the first memory device respectively, where the second pair of pixels are the first two pixels in a second vertical column of pixels in a frame and are horizontally adjacent to the first pair of pixels.

81. A method of storing pixel data and retrieving pixel data in a checkerboard buffer, comprising:

storing pixel data for a first pixel and a second pixel at a first memory address in a first memory device and a second memory device respectively, where the first pixel and the second pixel are the first two pixels in a first horizontal row of pixels in a frame;

storing pixel data for a third pixel and a fourth pixel at a second memory address in the second memory device and the first memory device respectively, where the third pixel and the fourth pixel are the first two pixels in a second horizontal row of pixels in a frame, and the third pixel and the fourth pixel are vertically adjacent to the first pixel and the second pixel, respectively;

retrieving pixel data for the first pixel and the third pixel from the first memory address in the first memory device and from the second memory address in the second memory device respectively, where the first pixel and the third pixel are the first two pixels in a first vertical column of pixels in a frame; and

retrieving pixel data for the second pixel and the fourth pixel from the first memory address in the second memory device and from the second memory address in the first memory device respectively, where the second pixel and the fourth pixel are the first two pixels in a second vertical column of pixels in a frame and the second pixel and the fourth pixel are horizontally adjacent to the first pixel and the third pixel, respectively.

82. The method of claim 81, further comprising:

providing pixel data from a first output of a video source and a second output of a video source to a data switch;

providing a source address to the first memory device and the second memory device, where the source address is a memory address;

controlling a state of the data switch, where in a first state the data switch provides pixel data from the first output of the video source to the first memory device and pixel data from the second output of the video source to the second memory device, and in a second state the data switch provides pixel data from the first output of the video source to the second memory device and pixel data from the second output of the video source to the first memory device, and where the state switches after storing pixel data for each horizontal row of pixels;

providing the pixel data from the data switch to the first memory device and the second memory device according to the state of the data switch; and

storing the pixel data in the first memory device and the second memory device at the source address.

83. The method of claim 81, further comprising:

generating a first destination address and a second destination address, where the destination address is a memory address;

providing the first destination address to the first memory device;

providing the second destination address to the second memory device;

controlling a state of a data switch, where in a first state the data switch provides pixel data from the first memory device to a first input of a data destination and pixel data from the second memory device to a second input of the data destination, and in a second state the data switch provides pixel data from the second memory device to the first input of the data destination and pixel data from the first memory device to the second input of the data destination, and where the state switches after retrieving pixel data for each vertical column of pixels;

providing pixel data from the first memory device stored at the first destination address to the data switch;

providing pixel data from the second memory device stored at the second destination address to the data switch, and

providing pixel data from the data switch to the data destination according to the state of the data switch.

84. The method of claim 81, where:

each memory device is divided into two memory sections, a first memory section for storing data and a second memory section for retrieving data;

a block of data is stored to the first memory sections of the memory devices and a block of data is retrieved from the second memory sections in alternation; and

the memory sections switch roles between storing and retrieving with each frame of pixel data.

85. A system for storing pixel data in a checkerboard buffer, comprising:

means for storing pixel data for a first pair of pixels at a first memory address in a first memory device and a second memory device respectively, where the first pair of pixels are the first two pixels in a first horizontal row of pixels in a frame; and

means for storing pixel data for a second pair of pixels at a second memory address in the second memory device and the first memory device respectively, where the second pair of pixels are the first two pixels in a second horizontal row of pixels in a frame and are vertically adjacent to the first pair of pixels.

86. A system for retrieving pixel data in a checkerboard buffer, comprising:

means for retrieving pixel data for a first pair of pixels from a first memory address in a first memory device and from a second memory address in a second memory device respectively, where the first pair of pixels are the first two pixels in a first vertical column of pixels in a frame; and

means for retrieving pixel data for a second pair of pixels from the first memory address in the second memory device and from the second memory address in the first memory device respectively, where the second pair of pixels are the first two pixels in a second vertical column of pixels in a frame and are horizontally adjacent to the first pair of pixels.

87. A system for storing pixel data and retrieving pixel data in a checkerboard buffer, comprising:

means for storing pixel data for a first pixel and a second pixel at a first memory address in a first memory device and a second memory device respectively, where the first pixel and the second pixel are the first two pixels in a first horizontal row of pixels in a frame;

means for storing pixel data for a third pixel and a fourth pixel at a second memory address in the second memory device and the first memory device respectively, where the third pixel and the fourth pixel are the first two pixels in a second horizontal row of pixels in a frame, and the third pixel and the fourth pixel are vertically adjacent to the first pixel and the second pixel, respectively;

means for retrieving pixel data for the first pixel and the third pixel from the first memory address in the first memory device and from the second memory address in the second memory device respectively, where the first pixel and the third pixel are the first two pixels in a first vertical column of pixels in a frame; and

means for retrieving pixel data for the second pixel and the fourth pixel from the first memory address in the second memory device and from the second memory address in the first memory device respectively, where the second pixel and the fourth pixel are the first two pixels in a second vertical column of pixels in a frame and the second pixel and the fourth pixel are horizontally adjacent to the first pixel and the third pixel, respectively.

88. A method of storing data and retrieving data in a checkerboard buffer, comprising:

storing a first data element and a second data element at a first memory address in a first memory device and a second memory device respectively;

storing a third data element and a fourth data element at a second memory address in the second memory device and the first memory device respectively;

retrieving the first data element and the third data element from the first memory address in the first memory device and from the second memory address in the second memory device respectively; and

retrieving the second data element and the fourth data element from the first memory address in the second memory device and from the second memory address in the first memory device respectively.