Chip lead frames

• US 20020110956A1
• Filed: 06/08/2001
• Published: 08/15/2002
• Est. Priority Date: 12/19/2000
• Status: Abandoned Application

• Current Assignee: Intel Corporation
• Original Assignee: Intel Corporation
• Inventors: Ichikawa, Kinya, Kumamoto, Takashi
• Application Number:
  US09/878,123
• Publication Number:
  US 20020110956A1
• Time in Patent Office: Days
• US Class Current: 438/108
• CPC Class Codes: H01L 21/4832 Etching a temporary substrate after encapsulation process to form leads
• CPC Class Codes: H01L 21/561 Batch processing
• CPC Class Codes: H01L 21/563 Encapsulation of active face of flip-chip device, e.g. underfilling or underencapsulation of flip-chip, encapsulation preform on chip or mounting substrate
• CPC Class Codes: H01L 21/565 Moulds
• CPC Class Codes: H01L 2221/68377 with parts of the auxiliary support remaining in the finished device
• CPC Class Codes: H01L 2224/0401 Bonding areas specifically adapted for bump connectors, e.g. under bump metallisation [UBM]
• CPC Class Codes: H01L 2224/13111 Tin [Sn] as principal constituent
• CPC Class Codes: H01L 2224/16225 the item being non-metallic, e.g. insulating substrate with or without metallisation
• CPC Class Codes: H01L 2224/29111 Tin [Sn] as principal constituent
• CPC Class Codes: H01L 2224/2919 with a principal constituent of the material being a polymer, e.g. polyester, phenolic based polymer, epoxy
• CPC Class Codes: H01L 2224/32225 the item being non-metallic, e.g. insulating substrate with or without metallisation
• CPC Class Codes: H01L 2224/45144 Gold (Au) as principal constituent
• CPC Class Codes: H01L 2224/48227 connecting the wire to a bond pad of the item
• CPC Class Codes: H01L 2224/48465 the other connecting portion not on the bonding area being a wedge bond, i.e. ball-to-wedge, regular stitch
• CPC Class Codes: H01L 2224/73203 Bump and layer connectors
• CPC Class Codes: H01L 2224/73204 the bump connector being embedded into the layer connector
• CPC Class Codes: H01L 2224/73265 Layer and wire connectors
• CPC Class Codes: H01L 2224/83102 using surface energy, e.g. capillary forces
• CPC Class Codes: H01L 2224/92125 the second connecting process involving a layer connector
• CPC Class Codes: H01L 23/3107 the device being completely enclosed
• CPC Class Codes: H01L 23/3128 : the substrate having spherical bumps for external connection
• CPC Class Codes: H01L 24/28 : Structure, shape, material or disposition of the layer connectors prior to the connecting process
• CPC Class Codes: H01L 2924/00 : Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
• CPC Class Codes: H01L 2924/00012 : Relevant to the scope of the group, the symbol of which is combined with the symbol of this group
• CPC Class Codes: H01L 2924/00014 : the subject-matter covered by the group, the symbol of which is combined with the symbol of this group, being disclosed without further technical details
• CPC Class Codes: H01L 2924/01005 : Boron [B]
• CPC Class Codes: H01L 2924/01006 : Carbon [C]
• CPC Class Codes: H01L 2924/01029 : Copper [Cu]
• CPC Class Codes: H01L 2924/01033 : Arsenic [As]
• CPC Class Codes: H01L 2924/0105 : Tin [Sn]
• CPC Class Codes: H01L 2924/01061 : Promethium [Pm]
• CPC Class Codes: H01L 2924/01074 : Tungsten [W]
• CPC Class Codes: H01L 2924/01075 : Rhenium [Re]
• CPC Class Codes: H01L 2924/01079 : Gold [Au]
• CPC Class Codes: H01L 2924/01082 : Lead [Pb]
• CPC Class Codes: H01L 2924/0132 : Binary Alloys
• CPC Class Codes: H01L 2924/01322 : Eutectic Alloys, i.e. obtained by a liquid transforming into two solid phases
• CPC Class Codes: H01L 2924/0665 : Epoxy resin
• CPC Class Codes: H01L 2924/10253 : Silicon [Si]
• CPC Class Codes: H01L 2924/12042 : LASER
• CPC Class Codes: H01L 2924/14 : Integrated circuits
• CPC Class Codes: H01L 2924/15747 : Copper [Cu] as principal constituent
• CPC Class Codes: H01L 2924/18161 : of a flip chip
• CPC Class Codes: H01L 2924/19041 : being a capacitor
• CPC Class Codes: H01L 2924/19043 : being a resistor
• CPC Class Codes: H01L 2924/19105 : in a side-by-side arrangement on a common die mounting substrate
• CPC Class Codes: H01L 2924/30107 : Inductance
• CPC Class Codes: H01L 2924/351 : Thermal stress

Abstract

Chip lead frames are made by disposing a die having terminals on a substrate surface to form a cavity between the die and the substrate and contacts between the terminals and the substrate. A compound is applied to the surface such that the compound enters that cavity and forms a layer on the upper substrate surface. The layer can impart sufficient rigidity to the assembly that the substrate can be etched to produce a lead frame. Also disclosed are devices that include a die, a lead frame, and a continuous network that can form a layer on the lead frame and fill the cavity between the die and the lead frame.

Claims

1. A device comprising:

a lead frame having conductive leads and an insulative composition interposed between the leads;

a die having a lower die surface that overlies a first region of the lead frame, is connected by contacts to the lead frame, and is spaced by a gap from the first region; and

a polymer composition that forms a continuous network that forms a layer that extends at least above the lower die surface and covers regions of the lead frame surface that are outside the first region and are not occupied by any component.

2. The device of claim 1 further comprising an insulative layer that at least partially fills the gap and covers the first region.

3. The device of claim 1 in which the continuous network extends at least 50% of the distance to an upper die surface from the lower die surface.

4. The device of claim 3 in which the continuous network forms a layer covering the upper die surface.

5. The device of claim 1 in which the leads have a pitch of less than 0.10 mm.

6. A device comprising:

a conductive substrate;

a die having a lower die surface that opposes a first region of the substrate, is connected by contacts to the substrate, and is spaced by a gap from the first region; and

a polymer composition that forms a network on a region of the substrate that extends at least above the lower die surface, the layer imparting sufficient rigidity to the device to maintain integrity of the contacts during etching of the substrate in the absence of a supporting frame.

7. The device of claim 6 in which the conductive substrate comprises etches that are filled with a resistive composition.

8. The device of claim 6 in which the substrate comprises half etches.

9. The device of claim 6 in which the layer extends at least to the upper die surface

10. A device comprising:

a lead frame;

a die having a lower die surface that overlies, is connected by contacts to, and is spaced by a gap from a first region of the lead frame;

a peripheral component also connected to the lead frame at a location other than in the first region; and

a polymer composition

that extends in a direction normal to the lead frame at least above the lower die surface and extends along a surface of the lead frame from the die to the peripheral component.

11. The device of claim 10 further comprising an insulative layer that at least partially fills gap and covers the first region.

12. The device of claim 10 in which the layer extends to a perimeter of the lead frame.

14. The method of claim 13 in which the layer extends at least to the surface of the die that opposes the substrate.

15. The method of claim 13 in which the layer extends along the plane of the substrate a distance that is at least the distance from the die lower surface to the die upper surface.

16. The method of claim 13 in which the layer extends to the perimeter of the substrate.

17. The method of claim 13 in which the applying comprises (1) surrounding the die and the upper substrate surface using a mold to form a mold cavity;

and (2) injecting the compound into the mold cavity.

18. The method of claim 17 in which a surface of the mold includes a film.

19. The method of claim 17 in which the compound is injected under a pressure of at least 1 MPa.

20. The method of claim 13 in which the compound comprises an epoxy.

21. The method of claim 13 further comprising etching the substrate to generate leads, each lead forming a conductive path from one of the contacts to a lead terminus.

22. The method of claim 21 further comprising applying an insulative composition that fills etched regions of the substrate.

24. The method of claim 23 in which the disposing comprises (1) applying a compound to the surface such that the compound forms a layer on the upper substrate surface, and (2) setting the compound to form a continuous network.

25. The method of claim 23 in which the substrate comprises half-etches that are backed by a substrate underlayer, and the etching comprises removing the substrate underlayer.

26. The method of claim 23 in which the disposing comprises disposing multiple dies, and the method further comprises dicing the etched conductive substrate.

27. The method of claim 24 in which the compound fills the cavity.

28. The method of claim 24 further comprising, prior to applying the compound to the surface, filling the cavity using an underfill composition.

29. The method of claim 23 in which the upper substrate surface is covered by an insulative layer that has excised regions adapted for receiving the terminals.

30. The method of claim 29 in which a gap is formed between the insulative layer the die, and the method further includes, prior to b), applying a compound to the surface of the insulative layer that opposes the die;

filling the gap with the compound; and

setting the compound to form a continuous polymer network.

13. A method comprising:

a) forming a gap between a die and a substrate to which the die is connected;

b) causing a compound to enter the gap and to form a layer on an upper surface of the substrate; and

c) setting the compound to generate a continuous, rigid network that extends within the gap and forms a layer surrounding the die perimeter.

23. A method comprising:

a) disposing a die having terminals on an upper substrate surface of a conductive substrate such that a cavity is formed between the die and the substrate and contacts are formed between the terminals and the conductive substrate; and

b) etching the conductive substrate to generate conductive leads.