Adapting scan-bist architectures for low power operation

• US 20020112199A1
• Filed: 03/09/2001
• Published: 08/15/2002
• Est. Priority Date: 03/09/2000
• Status: Active Grant

• Current Assignee: Texas Instruments, Inc.
• Original Assignee: Texas Instruments, Inc.
• Inventors: Whetsel, Lee D.
• Granted Patent: US 6,763,488 B2
• Time in Patent Office: Days
• US Class Current: 714/30
• CPC Class Codes: G01R 31/31721 Power aspects, e.g. power supplies for test circuits, power saving during test for scan test G01R31/318575
• CPC Class Codes: G01R 31/31723 Hardware for routing the test signal within the device under test to the circuits to be tested, e.g. multiplexer for multiple core testing, accessing internal nodes routing the test signal to or from the device under test G01R31/31926
• CPC Class Codes: G01R 31/31724 Test controller, e.g. BIST state machine for scan test G01R31/318555
• CPC Class Codes: G01R 31/3177 Testing of logic operation, e.g. by logic analysers
• CPC Class Codes: G01R 31/318536 Scan chain arrangements, e.g. connections, test bus, analog signals
• CPC Class Codes: G01R 31/318575 Power distribution; Power saving

Abstract

A Scan-BIST architecture is adapted into a low power Scan-BIST architecture. A generator 102, compactor 106, and controller 110 remain the same as in the known art. The changes between the known art Scan-BIST architecture and the low power Scan-BIST architecture involve modification of the known scan path into scan path 502, to insert scan paths A 506, B 508 and C 510, and the insertion of an adaptor circuit 504 in the control path 114 between controller 110 and scan path 502.

Claims

1. A process of adapting a synthesized scan-BIST architecture for low power operation comprising:

A. partitioning the scan path of said scan BIST architecture into multiple separate scan path sections, each section having a scan input and a scan output;

B. forming a connection between the scan inputs of each scan path section;

C. forming a selective connection between the scan outputs of each scan path section;

D. providing a scan control circuit having separate scan control outputs; and

E. forming separate connections between each of said separate control outputs and one of said scan path sections;

2. A scan BIST test circuit, within an integrated circuit, comprising:

A. a plurality of scan paths each having a scan input, scan output, and a control input;

B. a generator circuit having a control input and a stimulus data output;

C. a compactor circuit having a control input and a response data input;

D. a control circuit providing control output to said control inputs of said scan path, generator circuit, and compactor circuit;

E. a first connection formed between said stimulus data output of said generator circuit and all of said scan inputs of said plurality of scan paths; and

F. a second connection selectively formed between said response data input of said compactor circuit and ones of said scan outputs of said plurality of scan paths.

3. A scan BIST test configuration of a circuit, within an integrated circuit, comprising:

A. a scan path having a first control input;

B. a generator having a second control input;

C. a compactor having a third control input;

D. a first controller having first control output;

E. a second controller having a fourth control input and second control output;

F. a connection between said first control output and said second, third, and fourth control inputs; and

G. a connection between said second control output and said first control input.

4. A scan-BIST configuration of a circuit, within an integrated circuit, comprising:

A. a plurality of scan paths each having a scan data input for receiving data from a test pattern generator circuit, a scan data output for transmitting data to a test pattern compactor circuit, a scan clock input for clocking the scan path, and a scan enable input for controlling the capture and shift operation of the scan path,

B. a common connection formed between the scan enable inputs of each scan path,

C. a scan clock control circuit having separately controllable scan clock outputs, and;

D. separate connections formed between each of said separately controllable scan clock outputs and ones of said scan clock inputs, such that the shift operation of each scan path may be separately performed.