Method for supply voltage drop analysis during placement phase of chip design
First Claim
1. A method of designing an integrated circuit within a power grid comprising:
- characterizing circuits in a circuit library for supply currents and voltage ranges;
constructing a power grid model based on general power requirements of the integrated circuit under design;
calculating an impedance matrix representing impedance between ports in the power grid model;
assigning selected circuits from the library to the ports;
calculating current and voltage at each of the ports;
using a cost function to calculate the cost of placement of the assigned circuits; and
perturbing the assignment of the circuits, if the cost of such placement does not meet design requirements.
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Accused Products
Abstract
A method of analyzing supply voltage drops in a power grid for distributing power to an integrated circuit chip during design. The method initially comprises providing a library of circuits for use in designing an integrated circuit chip and determining a supply current requirement and an operating voltage range for each circuit in the circuit library. The method then includes calculating an admittance matrix representing the power grid with a pre-specified array of circuit ports defined by intersection of the power grid and a modeling grid, assigning regions of the power grid to each of the ports, and placing a set of circuits from the circuit library in regions on the power grid. The method further includes calculating a total node current at each of the ports by summing current requirements of all of the circuits located in the regions, calculating a node voltage at each of the ports by solving a system of linear equations corresponding to the calculated admittance matrix, imposing a penalty to each node having a node voltage outside of a predetermined range, and calculating the node voltages and the penalties to a cost-based floorplanning/placement analysis tool.
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Citations
22 Claims
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1. A method of designing an integrated circuit within a power grid comprising:
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characterizing circuits in a circuit library for supply currents and voltage ranges;
constructing a power grid model based on general power requirements of the integrated circuit under design;
calculating an impedance matrix representing impedance between ports in the power grid model;
assigning selected circuits from the library to the ports;
calculating current and voltage at each of the ports;
using a cost function to calculate the cost of placement of the assigned circuits; and
perturbing the assignment of the circuits, if the cost of such placement does not meet design requirements. - View Dependent Claims (2, 3, 4, 5, 6, 7, 8, 9)
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10. A method of analyzing supply voltage drops in a power grid for distributing power to an integrated circuit chip during design comprising:
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providing a library of circuits for use in designing an integrated circuit chip;
determining a supply current requirement and an operating voltage range for each circuit in the circuit library;
calculating an admittance matrix representing a passive power grid with a pre-specified array of circuit ports defined by intersection of the power grid and a modeling grid;
assigning regions of the power grid to each of the ports;
placing a set of circuits from the circuit library in regions on the power grid;
calculating a total node current at each of the ports by summing current requirements of all of the circuits located in the regions;
calculating a node voltage at each of the ports by solving a system of linear equations corresponding to the calculated admittance matrix;
imposing a penalty to each node having a node voltage outside of a predetermined range; and
writing the node voltages and the penalties to a cost-based floorplanning/placement analysis tool. - View Dependent Claims (11, 12, 14, 15, 17, 19, 20)
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13. A program storage device readable by a machine, tangibly embodying a program of instructions executable by the machine to perform method steps for designing an integrated circuit within a power grid using a library of circuits, said method steps comprising:
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characterizing circuits in the library for supply currents and voltage ranges;
constructing a power grid model based on general power requirements of the integrated circuit under design;
calculating an impedance matrix representing impedance between ports in the power grid model;
assigning selected circuits from the library to the ports;
calculating current and voltage at each of the ports;
using a cost function to calculate the cost of placement of the assigned circuits; and
perturbing the assignment of the circuits, if the cost of such placement does not meet design requirements.
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16. A program storage device readable by a machine, tangibly embodying a program of instructions executable by the machine to perform method steps for analyzing supply voltage drops in a power grid for distributing power to an integrated circuit chip during design the program utilizing a library of circuits employed in designing an integrated circuit chip, said method steps comprising:
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determining a supply current requirement and an operating voltage range for each circuit in the circuit library;
calculating an admittance matrix representing a passive power grid with a pre-specified array of circuit ports defined by intersection of the power grid and a modeling grid;
assigning regions of the power grid to each of the ports;
placing a set of circuits from the circuit library in regions on the power grid;
calculating a total node current at each of the ports by summing current requirements of all of the circuits located in the regions;
calculating a node voltage at each of the ports by solving a system of linear equations corresponding to the calculated admittance matrix;
imposing a penalty to each node having a node voltage outside of a predetermined range; and
writing the node voltages and the penalties to a cost-based floorplanning/placement analysis tool.
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18. A computer program product comprising a computer usable medium having computer readable program code means embodied therein for designing an integrated circuit within a power grid, the computer program product utilizing a library of circuits for use in designing an integrated circuit chip, the computer readable program code means in said computer program product comprising:
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computer readable program code means for characterizing the circuits in the library for supply currents and voltage ranges;
computer readable program code means for constructing a power grid model based on general power requirements of the integrated circuit under design;
computer readable program code means for calculating an impedance matrix representing impedance between ports in the power grid model;
computer readable program code means for assigning selected circuits from the library to the ports;
computer readable program code means for calculating current and voltage at each of the ports;
computer readable program code means for using a cost function to calculate the cost of placement of the assigned circuits; and
computer readable program code means for perturbing the assignment of the circuits, if the cost of such placement does not meet design requirements.
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21. A computer program product comprising a computer usable medium having computer readable program code means embodied therein for analyzing supply voltage drops in a power grid for distributing power to an integrated circuit chip during design, the computer program product utilizing a library of circuits employed in designing an integrated circuit chip, the computer readable program code means in said computer program product comprising:
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computer readable program code means for determining a supply current requirement and an operating voltage range for each circuit in the circuit library;
computer readable program code means for calculating an admittance matrix representing a passive power grid with a pre-specified array of circuit ports defined by intersection of the power grid and a modeling grid;
computer readable program code means for assigning regions of the power grid to each of the ports;
computer readable program code means for placing a set of circuits from the circuit library in regions on the power grid;
computer readable program code means for calculating a total node current at each of the ports by summing current requirements of all of the circuits located in the regions;
computer readable program code means for calculating a node voltage at each of the ports by solving a system of linear equations corresponding to the calculated admittance matrix;
computer readable program code means for imposing a penalty to each node having a node voltage outside of a predetermined range; and
computer readable program code means for writing the node voltages and the penalties to a cost-based floorplanning/placement analysis tool. - View Dependent Claims (22)
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Specification