Conductive coupling of electrical structures to a semiconductor device located under a buried oxide layer

• US 20020113267A1
• Filed: 02/16/2001
• Published: 08/22/2002
• Est. Priority Date: 02/16/2001
• Status: Active Grant

• Current Assignee: Globalfoundries US Incorporated (GlobalFoundries, Inc.)
• Original Assignee: International Business Machines Corporation
• Inventors: Tonti, William R., Rankin, Jed H., Gauthier, Robert J. Jr., Brown, Jeffrey S.
• Granted Patent: US 6,498,372 B2
• Time in Patent Office: Days
• US Class Current: 257/355
• CPC Class Codes: H01L 21/743 Making of internal connections, substrate contacts
• CPC Class Codes: H01L 21/763 Polycrystalline semiconductor regions H01L21/76264 takes precedence
• CPC Class Codes: H01L 27/0251 for MOS devices

Abstract

A method and structure for conductively coupling electrical structures to a semiconductor device located under a silicon on insulator (SOI) layer. The SOI layer is formed on a bulk semiconductor substrate. A trench structure through the SOI layer is formed, wherein an end of the trench structure interfaces with the bulk semiconductor substrate. A semiconductor device is formed in the bulk semiconductor substrate, wherein the semiconductor device includes P⁺ and N⁺ diffusions. Conductive plugs are formed through the trench structure such that the conductive plugs are self-aligned with, and in conductive contact with, the diffusions. The semiconductor device in the bulk semiconductor substrate may include an electrostatic discharge device (ESD). The bulk semiconductor substrate, which has a high thermal conductivity, serves as an effective medium for dissipating heat generated by the ESD.

Claims

1. An electronic structure, comprising:

a bulk semiconductor substrate having a semiconductor device, wherein the semiconductor device includes M diffusions, wherein M is at least 2, wherein a first diffusion of the M diffusions is a P⁺ diffusion, and wherein a second diffusion of the M diffusions is a N⁺ diffusion;

a silicon-on-insulator (SOI) structure on the bulk semiconductor substrate, wherein the SOI structure includes an insulator layer on the bulk semiconductor substrate and a semiconductor layer on the insulator layer; and

M conductive plugs self-aligned with the M diffusions and extending through a portion of the SOI layer such that an end of each conductive plug is in conductive contact with a corresponding diffusion of the M diffusions.

2. The electronic structure of claim 1, wherein each conductive plug includes a conductive material selected from the group consisting of intrinsic polysilicon, doped polysilicon, tungsten, and aluminum.

3. The electronic structure of claim 1, wherein each conductive plug is of a same conductivity type as the corresponding diffusion.

4. The electronic structure of claim 1, wherein the each diffusion has been formed by implantation of dopant.

5. The electronic structure of claim 1, wherein each conductive plug is a through plug.

6. The electronic structure of claim 1, wherein each conductive plug is a spacer plug.

7. The electronic structure of claim 1, further comprising an insulative liner structure which insulatively separates each conductive plug from the semiconductor layer.

8. The electronic structure of claim 1, wherein the semiconductor device includes an electrostatic discharge device (ESD).

9. The electronic structure of claim 1, wherein the semiconductor device includes a diode or a diffusion capacitor.

10. The electronic structure of claim 1, wherein the bulk semiconductor substrate includes a doped well, and wherein a portion of the semiconductor device is within the doped well.

11. The electronic structure of claim 1, further comprising M conductive nodes and M conductive interfaces, wherein each interface of the M conductive interfaces is in conductive contact with a corresponding conductive plug of the M conductive plugs and a corresponding conductive node of the M conductive nodes.

12. The electronic structure of claim 1, wherein M is at least 3, wherein a third diffusion of the M diffusions is a N⁺ diffusion or a P⁺ diffusion, and wherein the semiconductor device includes a bipolar transistor.

13. The electronic structure of claim 1, wherein M is at least 4, wherein a third diffusion of the M diffusions is a P⁺ diffusion, wherein a fourth diffusion of the M diffusions is a N⁺ diffusion, and wherein the semiconductor device includes a thyristor.

15. The method of claim 14, wherein each conductive plug includes a conductive material selected from the group consisting of intrinsic polysilicon, doped polysilicon, tungsten, and aluminum.

16. The method of claim 14, wherein each conductive plug is of a same conductivity type as the corresponding diffusion.

17. The method of claim 14, wherein the step of forming a semiconductor device includes forming each diffusion by implantation of dopant.

18. The method of claim 14, wherein each conductive plug is a through plug.

19. The method of claim 14, wherein each conductive plug is a spacer plug.

20. The method of claim 14, further comprising forming an insulative liner structure which insulatively separates each conductive plug from the semiconductor layer.

21. The method of claim 14, wherein the semiconductor device includes an electrostatic discharge device (ESD).

22. The method of claim 14, wherein the semiconductor device includes a diode or a diffusion capacitor.

23. The method of claim 14, wherein the bulk semiconductor substrate includes a doped well, and wherein a portion of the semiconductor device is within the doped well.

24. The method of claim 14, further comprising further comprising forming M conductive nodes and M conductive interfaces, wherein each interface of the M conductive interfaces is in conductive contact with a corresponding conductive plug of the M conductive plugs and a corresponding conductive node of the M conductive nodes.

25. The method of claim 14, wherein M is at least 3, wherein a third diffusion of the M diffusions is a N⁺ diffusion or a P⁺ diffusion, and wherein the semiconductor device includes a bipolar transistor.

26. The method of claim 14, further comprising wherein M is at least 4, wherein a third diffusion of the M diffusions is a P⁺ diffusion, wherein a fourth diffusion of the M diffusions is a N⁺ diffusion, and wherein the semiconductor device includes a thyristor.

14. A method for forming an electronic structure, comprising the steps of:

providing a bulk semiconductor substrate;

forming a silicon-on-insulator (SOI) structure on the bulk semiconductor substrate, wherein the SOI structure includes an insulator layer on the bulk semiconductor substrate and a semiconductor layer on the insulator layer;

forming a trench structure through the SOI layer, wherein an end of the trench structure is interfaced with the bulk semiconductor substrate;

forming a semiconductor device in the bulk semiconductor substrate by use of the trench structure, wherein the semiconductor device includes M diffusions, wherein M is at least 2, wherein a first diffusion of the M diffusions is a P⁺ diffusion, and wherein a second diffusion of the M diffusions is a N⁺ diffusion; and

forming M conductive plugs self-aligned with the M diffusions and extending through a portion of the SO layer such that an end of each conductive plug is in conductive contact with a corresponding diffusion of the M diffusions.