Data driving circuit of liquid crystal display device

• US 20020113762A1
• Filed: 01/03/2002
• Published: 08/22/2002
• Est. Priority Date: 02/19/2001
• Status: Active Grant

• Current Assignee: LG Display Co., Ltd.
• Original Assignee: LG Philips LCD Company Limited (LG Display Co., Ltd.)
• Inventors: Ha, Yong Min
• Granted Patent: US 7,133,011 B2
• Time in Patent Office: Days
• US Class Current: 345/87
• CPC Class Codes: G09G 2330/021 Power management, e.g. power saving
• CPC Class Codes: G09G 3/2011 by amplitude modulation
• CPC Class Codes: G09G 3/3688 suitable for active matrices only

Abstract

A data driving circuit of an LCD device includes a timing controller for formatting input data so that data and gate drivers of an LCD panel display a picture image, and outputting a selection signal; a plurality of digital to analog converters for converting digital signals output from the timing controller to analog signals based on a color gray level displayed; and a plurality of amplifiers for amplifying the signals output from the respective digital to analog converters and outputting the amplified signals to the LCD panel.

Claims

1. A data driving circuit of an LCD device comprising:

a timing controller for formatting input data so that data and gate drivers of an LCD panel display a picture image, and outputting a selection signal;

a plurality of digital to analog converters for converting digital signals output from the timing controller to analog signals based on a color gray level displayed; and

a plurality of amplifiers for amplifying the signals output from the respective digital to analog converters and outputting the amplified signals to the LCD panel.

2. The data driving circuit of the LCD device as claimed in claim 1, further comprising a plurality of multiplexers for selecting a signal output from one of the digital to analog converters in accordance with the selection signal of the timing controller and outputting the selected signal to the LCD panel.

3. The data driving circuit of the LCD device as claimed in claim 1, comprising a first digital to analog converter and a second digital to analog converter, the first digital to analog converter serving to obtain a multigray (64 gray or 6 bit) image, and the second digital to analog converter serving to obtain a low gray (2 gray, 1 bit) image.

4. The data driving circuit of the LCD device as claimed in claim 1, comprising a first digital to analog converter, a second digital to analog converter and a third digital to analog converter, the first digital to analog converter serving to obtain a multigray (64 gray or 6 bit) image, the second digital to analog converter serving to obtain an intermediate gray (16 gray or 4 bit) image, and the third digital to analog converter serving to obtain a low gray (2 gray or 1 bit) image.

5. A data driving circuit of an LCD device comprising:

a timing controller for formatting input data so that data and gate drivers of an LCD panel display a picture image, and outputting a selection signal;

a level shifter for amplifying voltage levels of signals output from the timing controller;

a plurality of digital to analog converters for converting digital signals output from the level shifter to analog signals based on a color gray level displayed;

a plurality of amplifiers for amplifying the signals output from the respective digital to analog converters and outputting the amplified signals to the LCD panel; and

a plurality of multiplexers for selecting a signal output from one of the plurality of amplifiers in accordance with the selection signal of the timing controller and outputting the selected signal to the LCD panel.

6. The data driving circuit of the LCD device as claimed in claim 5, comprising a first digital to analog converter and a second digital to analog converter, the first digital to analog converter serving to obtain a multigray (64 gray or 6 bit) image, and the second digital to analog converter serving to obtain a low gray (2 gray, 1 bit) image.

7. The data driving circuit of the LCD device as claimed in claim 5, comprising a first digital to analog converter, a second digital to analog converter and a third digital to analog converter, the first digital to analog converter serving to obtain a multigray (64 gray or 6 bit) image, the second digital to analog converter serving to obtain an intermediate gray (16 gray or 4 bit) image, and the third digital to analog converter serving to obtain a low gray (2 gray or 1 bit) image.