LSI having interpreter function and information recording/reproducing apparatus using the same

• US 20020114457A1
• Filed: 01/18/2002
• Published: 08/22/2002
• Est. Priority Date: 01/26/2001
• Status: Abandoned Application

• Current Assignee: Matsushita Electric Industrial Company Limited (Panasonic Holdings Corporation)
• Original Assignee: Matsushita Electric Industrial Company Limited (Panasonic Holdings Corporation)
• Inventors: Sato, Takahiro, Usui, Makoto, Ito, Motoshi, Yabuno, Hiroyuki
• Application Number:
  US10/051,585
• Publication Number:
  US 20020114457A1
• Time in Patent Office: Days
• US Class Current: 380/201
• CPC Class Codes: G11B 20/00086 Circuits for prevention of unauthorised reproduction or copying, e.g. piracy indicating unauthorised use of record carriers in general G11B23/28; scrambling for television signal recording H04N5/913; network architectures or network protocols for network security H04L63/00; cryptographic mechanisms or cryptographic arrangements for secret or secure communication H04L9/00
• CPC Class Codes: G11B 20/0021 involving encryption or decryption of contents recorded on or reproduced from a record carrier
• CPC Class Codes: G11B 20/00224 wherein the key is obtained from a remote server
• CPC Class Codes: G11B 20/00775 wherein said copy control information is encoded in an encryption mode indicator [EMI]
• CPC Class Codes: G11B 20/10 Digital recording or reproducing
• CPC Class Codes: G11B 2020/1259 with ROM/RAM areas

Abstract

An LSI comprises: a RAM for storing an intermediate code; a ROM for storing an interpreter execution program that is capable of interpreting the intermediate code; and a CPU for controlling execution of the interpreter execution program, wherein the RAM, the ROM, and the CPU are formed on one chip.

Claims

1. An LSI, comprising:

a RAM for storing an intermediate code;

a ROM for storing an interpreter execution program that is capable of interpreting the intermediate code; and

a CPU for controlling execution of the interpreter execution program,

wherein the RAM, the ROM, and the CPU are formed on one chip.

2. An LSI according to claim 1, wherein the intermediate code is encrypted.

3. An LSI according to claim 1, wherein:

the RAM can store an encrypted intermediate code and an unencrypted intermediate code; and

the interpreter execution program can interpret both the encrypted intermediate code and the unencrypted intermediate code.

4. An LSI according to claim 1, further comprising:

a recording/reproduction head for recording/reproducing information on an optical disc; and

an optical disc control section for controlling a motor which drives the optical disc,

wherein the optical disc control section is formed on the one chip.

5. An optical disc apparatus, comprising:

an execution section for executing an interpreter execution program that is capable of interpreting an intermediate code, so as to generate a control command string; and

a control section for controlling recording/reproduction of information on an optical disc according to the control command string.

6. An optical disc apparatus according to claim 5, wherein the execution section includes:

a RAM for storing an intermediate code;

a ROM for storing the interpreter execution program; and

a CPU for controlling execution of the interpreter execution program.

7. An optical disc apparatus according to claim 6, wherein the RAM, the ROM, and the CPU are formed on one chip.

8. An optical disc apparatus according to claim 7, wherein the control section includes:

a recording/reproduction head for recording/reproducing information on the optical disc;

a motor for driving the optical disc; and

an optical disc control section for controlling the recording/reproduction head and the motor.

9. An optical disc apparatus according to claim 8, wherein the optical disc control section is formed on the one chip.

10. An optical disc apparatus according to claim 5, wherein the intermediate code is encrypted.

11. An optical disc apparatus according to claim 6, wherein:

the RAM can store an encrypted intermediate code and an unencrypted intermediate code; and

the interpreter execution program can interpret both the encrypted intermediate code and the unencrypted intermediate code.