Dielectric interface films and methods therefor

• US 20020115252A1
• Filed: 08/31/2001
• Published: 08/22/2002
• Est. Priority Date: 10/10/2000
• Status: Active Grant

• Current Assignee: ASM International NV
• Original Assignee: ASM International NV
• Inventors: Tuominen, Marko, Skarp, Jarmo, Haukka, Suvi P.
• Granted Patent: US 6,660,660 B2
• Time in Patent Office: Days
• US Class Current: 438/240
• CPC Class Codes: C23C 16/40 Oxides
• CPC Class Codes: C23C 16/403 of aluminium, magnesium or beryllium
• CPC Class Codes: C23C 16/45529 specially adapted for making a layer stack of alternating different compositions or gradient compositions
• CPC Class Codes: H01L 21/02178 the material containing aluminium, e.g. Al2O3
• CPC Class Codes: H01L 21/02189 the material containing zirconium, e.g. ZrO2
• CPC Class Codes: H01L 21/02192 the material containing at least one rare earth metal element, e.g. oxides of lanthanides, scandium or yttrium
• CPC Class Codes: H01L 21/02194 the material containing more than one metal element
• CPC Class Codes: H01L 21/022 the layer being a laminate, i.e. composed of sublayers, e.g. stacks of alternating high-k metal oxides adhesion layers or buffer layers H01L21/02304, H01L21/02362
• CPC Class Codes: H01L 21/0228 deposition by cyclic CVD, e.g. ALD, ALE, pulsed CVD
• CPC Class Codes: H01L 21/02299 pre-treatment
• CPC Class Codes: H01L 21/3142 of nano-laminates, e.g. alternating layers of Al203-Hf02
• CPC Class Codes: H01L 21/31604 Deposition from a gas or vapour H01L21/31691, H01L21/31695 take precedence
• CPC Class Codes: H01L 21/3162 on a silicon body
• CPC Class Codes: H01L 28/56 the dielectric comprising two or more layers, e.g. comprising buffer layers, seed layers, gradient layers
• CPC Class Codes: H01L 29/513 the variation being perpendicular to the channel plane
• CPC Class Codes: H01L 29/517 the insulating material comprising a metallic compound, e.g. metal oxide, metal silicate H01L29/518 takes precedence
• CPC Class Codes: Y10S 977/891 Vapor phase deposition

Abstract

An ultrathin aluminum oxide and lanthanide layers, particularly formed by an atomic layer deposition (ALD) type process, serve as interface layers between two or more materials. The interface layers can prevent oxidation of a substrate and can prevent diffusion of molecules between the materials. In the illustrated embodiments, a high-k dielectric material is sandwiched between two layers of aluminum oxide or lanthanide oxide in the formation of a transistor gate dielectric or a memory cell dielectric. Aluminum oxides can serve as a nucleation layer with less than a full monolayer of aluminum oxide. One monolayer or greater can also serve as a diffusion barrier, protecting the substrate from oxidation and the high-k dielectric from impurity diffusion. Nanolaminates can be formed with multiple alternating interface layers and high-k layers, where intermediate interface layers can break up the crystal structure of the high-k materials and lower leakage levels.

Claims

1. An integrated circuit comprising an interface layer between a conductive material and a dielectric material, the interface layer selected from the group consisting of aluminum oxide and lanthanide oxides and having a thickness less than or equal to about 4 molecular monolayers.

2. The integrated circuit of claim 1, wherein the conductive material comprises silicon.

3. The integrated circuit of claim 1, wherein the conductive material is a single-crystal silicon structure.

4. The integrated circuit of claim 1, wherein the conductive material is a silicon-germanium alloy.

5. The integrated circuit of claim 1, wherein the dielectric material is characterized by a dielectric constant greater than about 10.

6. The integrated circuit of claim 5, further comprising a second interface layer directly contacting an opposite side of the dielectric material, and a second conductive material directly over the second interface layer, the second interface layer selected from the group consisting of aluminum oxide and lanthanide oxides and having a thickness of less than or equal to about 4 molecular monolayers.

7. The integrated circuit of claim 6, wherein the conductive material comprises a silicon substrate, wherein the second conductive material comprises a gate electrode, and wherein the interface layer, dielectric material and second interface layer form a gate dielectric for an integrated transistor.

8. The integrated circuit of claim 6, wherein the conductive material comprises a storage electrode in a memory cell, and the second conductive material comprises a reference electrode, wherein the interface layer, dielectric material and second interface layer form a capacitor dielectric for an integrated capacitor.

9. The integrated circuit of claim 5, wherein the interface layer has a thickness between about 3 Å

and 15 Å

.

10. The integrated circuit of claim 9, wherein the interface layer has a thickness between about 3 Å

and 9 Å

.

11. The integrated circuit of claim 1, further comprising a plurality of alternating interface and dielectric layers, each interface layer selected from the group consisting of aluminum oxide and lanthanide oxides and having a thickness between about 1 Å

and 15 Å

, each dielectric layer having a dielectric constant of greater than about 5.

12. The integrated circuit of claim 11, wherein each interface layer comprises aluminum oxide and each dielectric layer comprises zirconium oxide.

14. The high-k dielectric structure of claim 13, wherein the high-k material is selected from the group consisting of zirconium oxide (ZrO₂), titanium oxide (TiO₂), tantalum oxide (Ta₂O₅), barium strontium titanate (BST), strontium titanate (ST), barium titanate (BT), lead zirconium titanate (PZT), and strontium bismuth tantalate (SBT).

15. The high-k dielectric structure of claim 13, wherein each of the first aluminum oxide layer and the second aluminum oxide layer have a thickness of less than or equal to about two monolayers.

17. The capacitor structure of claim 16, wherein the oxide layers are deposited by ALD.

18. The capacitor structure of claim 16, wherein the first conductor comprises a single-crystal silicon substrate.

19. The capacitor structure of claim 16, wherein the dielectric material has a dielectric constant of at least about 5.

20. The capacitor structure of claim 19, wherein the dielectric material is selected from the group consisting of zirconium oxide (ZrO₂), hafnium oxide (HfO₂), titanium oxide (TiO₂), tantalum oxide (Ta₂O₅), barium strontium titanate (BST), strontium titanate (ST), barium titanate (BT), lead zirconium titanate (PZT), lead strontium titanate (PST), strontium bismuth tantalate (SBT), tantalum oxynitride (Ta_xO_yN_z) and niobium oxynitride (Nb_xO_yN_z).

21. The capacitor structure of claim 16, wherein the second conductor is a transistor gate electrode comprising SiGe.

22. The capacitor structure of claim 16, wherein the second conductor directly contacts the second oxide layer.

25. The method of claim 24, wherein the layer of aluminum oxide has a thickness between about 3 Å

and 15 Å

.

26. The method of claim 24, wherein forming the layer of aluminum oxide comprises depositing the layer of aluminum oxide on the substrate by an ALD type process.

27. The method of claim 26, further comprising exposing the substrate to an ALD preparation pulse prior to depositing the layer of aluminum oxide by the ALD type process.

28. The method of claim 27, wherein the ALD preparation pulse comprises providing a mild oxidant over a hydrogen terminated surface of the substrate.

29. The method of claim 28, wherein the mild oxidant comprises water.

30. The method of claim 24, wherein forming the layer of aluminum oxide on the substrate comprises exposing a silicon oxide layer on the substrate to an aluminum halide.

31. The method of claim 30, wherein the aluminum halide comprises AlCl_3.

32. The method of claim 30, wherein exposing the silicon oxide layer on the substrate to an aluminum halide completely converts the silicon oxide layer to aluminum oxide by an exchange reaction.

13. A high-k dielectric structure in an integrated circuit comprising a first aluminum oxide layer, a high-k material layer directly over the first aluminum oxide layer, and a second layer of aluminum oxide directly over the high-k material layer, wherein the high-k material layer is characterized by a dielectric constant greater than about 5.

16. A capacitor structure in an integrated circuit, comprising:

a first conductor;

a first oxide layer directly overlying the first conductor, the first oxide layer comprising a material selected from the group consisting of aluminum oxide and lanthanide oxides;

a dielectric material directly overlying the first oxide layer;

a second oxide layer directly overlying the dielectric material, the second oxide layer comprising a material selected from the group consisting of aluminum oxide and lanthanide oxides; and

a second conductor overlying the second oxide layer.

23. An oxide layer located between two materials, wherein the oxide layer prevents diffusion of molecules from one material to the other, the oxide layer selected from the group consisting of aluminum oxide and lanthanide oxides, the oxide layer having a thickness between one full molecular monolayer and about 4 molecular monolayers.

24. A method of preventing the oxidation of a substrate during high-k material deposition, comprising:

forming a layer of aluminum oxide on the substrate; and

depositing the high-k material, having a dielectric constant greater than about 5, directly over the aluminum oxide layer.

33. A process for forming a dielectric stack in an integrated circuit, the process comprising at least one of the following cycle:

forming no more than about one monolayer of an aluminum or lanthanide complex over a semiconductor substrate by exposure to a first reactant species;

reacting an oxygen source gas with the first material to leave no more than about one monolayer of aluminum oxide or lanthanide oxide over the semiconductor substrate.

34. The process of claim 33, further comprising repeating the cycle between about 3 and 15 times to form an aluminum oxide or lanthanide oxide interface layer.

35. The process of claim 34, further comprising depositing a dielectric material with a dielectric constant of at least about 5 directly over the interface layer.

36. The process of claim 35, further comprising repeating the cycle at least once after depositing the dielectric material to form a top aluminum oxide or lanthanide oxide interface layer.

37. The process of claim 36, further comprising depositing a silicon-containing layer over the second interface layer.

39. The dielectric nanolaminate structure of claim 38, wherein the crystalline metal oxide comprises a material having a dielectric constant greater than about 10.

40. The dielectric nanolaminate structure of claim 38, wherein the crystalline metal oxide comprises an oxide of a metal in one of groups 4 and 5 of the periodic table of elements.

41. The dielectric nanolaminate structure of claim 38, wherein each amorphous metal oxide has a thickness between about 3 Å

and 15 Å

.

38. A dielectric nanolaminate structure, comprising at least three alternating layers of crystalline and amorphous metal oxides, including amorphous metal oxide layers on outside surfaces of the nanolaminate structure.

42. A nanolaminate structure, comprising at least two high-k layers separated by an intermediate oxide layer selected from the group consisting of aluminum oxide and lanthanide oxides, the high-k layers each characterized by a dielectric constant greater than about 10, the intermediate oxide layer having a thickness of no more than about 10 Å

.

43. The nanolaminate structure of claim 42, further comprising outer oxide layers on an outer side of each of the two high-k layers, the outer oxide layers selected from the group consisting of aluminum oxide and lanthanide oxides and having thicknesses of no more than about 4 molecular monolayers.

44. The nanolaminate structure of claim 43, wherein the outer oxide layers have thicknesses between about 1 molecular monlayer and 2 molecular monlayers.

45. The nanolaminate structure of claim 43, wherein the outer oxide layers have a thickness of about 10 Å

and the intermediate oxide layer has a thickness of about 5 Å

..