METHOD AND SYSTEM FOR DESIGN VERIFICATION OF ELECTRONIC CIRCUITS

• US 20020116168A1
• Filed: 11/15/1999
• Published: 08/22/2002
• Est. Priority Date: 11/17/1998
• Status: Active Grant

• Current Assignee: Mahn Bok Kim
• Original Assignee: Mahn Bok Kim
• Inventors: KIM, MAHN BOK
• Granted Patent: US 6,571,370 B2
• Time in Patent Office: Days
• US Class Current: 703/28
• CPC Class Codes: G06F 30/331 with hardware acceleration, e.g. by using field programmable gate array [FPGA] or emulation

Abstract

The present invention discloses an emulation system and method. The present invention comprises a control FPGA with a bi-direction interface means, a target FPGA, a microcomputer, and a data storage unit.

Further, the present invention further comprises an option board mounted on the motherboard through a connector.

Consequently, it becomes possible to implement both downloading of netlist data and monitoring of the emulation system through a single cable.

Claims

1. An emulation system for emulating a circuit design comprising:

a computer installed with software for emulating said circuit design;

a target FPGA for configuring said circuit design;

a microcomputer;

a control FPGA for controlling and monitoring said target FPGA and said microcomputer;

a data storage unit for storing program and data of said microcomputer;

an interface through which said circuit design is downloaded; and

a cable connecting said computer to said interface.

2. The emulation system as claimed in claim 1, wherein said control FPGA receives the netlist data and said microcomputer program from said computer and stores them, thereafter enabling said target FPGA to initiate the emulation by resetting said target FPGA and said microcomputer.

3. The emulation system as claimed in claim 1, wherein said interface comprises either one or the combination from the group of a parallel port, RS232 serial port, USB interface, IEEE 1394 interface, PCMCIA, and PC option card.

4. The emulation system as claimed in claim 1, wherein said target FPGA is configured with the netlists of said circuit design.

5. The emulation system as claimed in claim 1, wherein said control FPGA transfers said netlist data for configuration to said data storage unit connected to said target FPGA and let said microcomputer configure the emulation circuits by fetching said netlist data from said data storage unit.

6. The emulation system as claimed in claim 1, wherein said control FPGA comprises FIFO internally in which the status of a selected signal of said target FPGA is stored.

7. The emulation system as claimed in claim 1, wherein said control FPGA comprises an external data storage unit in which the status of a selected signal of said of said target FPGA is stored.

8. The emulation system as claimed in claim 1, wherein said control FPGA distributes multiple of clock signals generated from said computer.

9. The emulation system as claimed in claim 1, wherein said target FPGA further comprises:

a display unit displaying the operation of said emulation system;

a data storage unit for storing circuit operation; and

a connector for an option board mounted on said emulation system.

10. The emulation system as claimed in claim 1, wherein said emulation system further comprises a DSP unit.

11. The emulation system as claimed in claim 1, wherein said cable comprises a means for configuring said target FPGA without said control FPGA.

12. The emulating system as claimed in claim 1, wherein said cable comprises a debugging means for monitoring the operation of said emulation system.

13. The emulation system as claimed in claim 1, wherein said cable comprises a clock generating means.

14. The emulation system as claimed in claim 1, wherein said target FPGA comprises a downloading signal bus for configuring said circuit design and a probing signal bus for verifying the configured circuit.

15. The emulation system as claimed in claim 1, wherein said control FPGA monitors and reports the command address of said microcomputer to said computer, thereby enabling the user to trace the execution of the program of said emulation software.

17. The emulation system as claimed in claim 16, wherein the number of pins between said connector and said target FPGA is different from each other.

18. The emulation system as claimed in claim 16, wherein the pin header of said connector is protruded to a direction of said option board where said target FPGA is soldered.

19. The emulation system as claimed in claim 16, wherein said option board comprises a header type connector for monitoring signals.

16. An emulation system for emulating a circuit design comprising:

a computer installed with software for emulating said circuit design;

an option board including a target FPGA;

a motherboard on which said option board is mounted; and

a connector for mounting said option board on said motherboard.

20. A method for emulating a circuit design comprising steps of:

designing a circuit on a computer installed with emulation software;

downloading the netlist data to a target FPGA through a control FPGA;

applying a stimulus to said target FPGA on said computer;

monitoring the response to said stimulus; and

displaying the response of said target FPGA on the screen of said computer.

21. The method as claimed in claim 20, wherein said step of applying said stimulus comprises steps of:

assigning a clock signal from control signals; and

applying said clock signal on the computer.

22. The method as claimed in claim 20, wherein said step of applying said stimulus comprises steps of:

generating said stimulus in a table format;

applying said stimulus to said target FPGA;

accessing a response to said stimulus in a table format; and

displaying said response on the screen of said computer.

23. The method as claimed in claim 22, wherein said step of generating said stimulus in a table format comprises an editing step with a graphic editor on the computer.

24. The method as claimed in claim 22, wherein said step of generating said stimulus in a table format further comprises a step of storing said stimulus in a CMD file format.

25. The method as claimed in claim 20, wherein said emulation method further comprises steps of:

storing the values of test vector in a data storage unit;

applying said test vector to said target FPGA;

storing the values of response vector in said data storage unit; and

comparing the values of said response vector with predefined values.

26. The method as claimed in claim 20, wherein said step of monitoring said response to said stimulus comprises a monitoring step with one or the combination from the group of TDI, TDO, TCK, TMS, and TRST of JTAG 1149.1 standard.

27. The method as claimed in claim 24, wherein said CMD file format comprises a table format or a file format.

28. The method as claimed in claim 20, wherein said monitoring step comprises a step of stopping the operation of said emulation system depending on the comparison with the predefined value.

29. The method as claimed in claim 28, wherein said predefined value is set from the computer.

30. The method as claimed in claim 28, wherein said predefined value is stored in said data storage unit on said motherboard.