Failure supervising method and apparatus

• US 20020116670A1
• Filed: 10/17/2001
• Published: 08/22/2002
• Est. Priority Date: 02/22/2001
• Status: Abandoned Application

• Current Assignee: Hitachi, Ltd.
• Original Assignee: Hitachi, Ltd.
• Inventors: Ukai, Hiroki, Arai, Toshiaki, Sato, Masahide, Oshima, Satoshi
• Application Number:
  US09/978,183
• Publication Number:
  US 20020116670A1
• Time in Patent Office: Days
• US Class Current: 714/55
• CPC Class Codes: G06F 11/0712 in a virtual computing platform, e.g. logically partitioned systems
• CPC Class Codes: G06F 11/0724 in a multiprocessor or a multi-core unit multiprocessors per se G06F15/80
• CPC Class Codes: G06F 11/0757 by exceeding a time limit, i.e. time-out, e.g. watchdogs
• CPC Class Codes: G06F 11/0793 Remedial or corrective actions recovery from an exception in an instruction pipeline G06F9/3861; by retry G06F11/1402; for recovering from a failure of a protocol instance or entity H04L69/40

Abstract

A failure supervising method and apparatus are disclosed. Simply with a WDT by which a system is interrupted after the WDT goes time out, the system would stop in a serious case where the failure cannot be recovered from by the interruption alone. A plurality of stages of WDTs are operatively interlocked, and the interlocked WDTs interrupt the system strongly progressively in each of the stages. A small failure recoverable by an interrupt is recovered by an interrupt, a middle failure not recoverable by other than a non-maskable interrupt is recovered by a non-maskable interrupt, and a serious failure not recoverable by other than reactivation is recovered by resetting the system.

Claims

1. A method of supervising a failure of a system using a timer, comprising the steps of:

(a) activating said timer and determining whether said timer is reset or not;

(b) counting down said timer if not reset;

(c) determining whether said timer has gone time out at a predetermined time;

(d) generating a signal for recovery from the failure in the case where said timer has gone time out; and

(e) repetitively executing said steps (a) to (d) for the next timer in the case where the failure cannot be recovered from.

2. A failure supervising method according to claim 1, wherein in accordance with the signal generated in step (d), the step of setting a flag, the step of outputting an interrupt signal, the step of outputting a non-maskable interrupt and the step of outputting a system reset signal are sequentially executed, thereby recovering from the failure in accordance with the degree of the failure progressively each time said step (e) is executed.

3. A failure supervising method according to claim 1, wherein a plurality of conditions are set for resetting said timer, and the timer reset operation and the corresponding one of said conditions are combined each time said step (e) is executed.

4. A failure supervising method according to claim 1, wherein the step executed in accordance with said signal generated in said step (d) is recorded.

5. An apparatus for supervising a failure of a system using a timer, comprising:

(a) means for activating said timer and determining whether said timer is reset or not;

(b) means for counting down said timer if not reset;

(c) means for determining whether said timer has gone time out at a predetermined time;

(d) means for generating a signal for recovery from the failure in the case where said timer has gone time out; and

(e) means for repetitively activating said means (a) to (d) for the next timer in the case where the failure cannot be recovered from.

6. A failure supervising apparatus according to claim 5,

wherein in accordance with the signal generated from said signal generating means, the step of setting a flag, the step of outputting an interrupt signal, the step of outputting a non-maskable interrupt and the step of outputting a system reset signal are sequentially executed, thereby recovering from the failure in accordance with the degree of the failure each time said repetitively activating means (e) is activated.

7. A failure supervising apparatus according to claim 5,

wherein a plurality of conditions are set for resetting said timer, and the timer reset operation and the corresponding one of said conditions are combined each time said repetitively activating means is activated.

8. A failure supervising apparatus according to claim 5,

wherein said signal generating means includes means for recording the step executed in accordance with said generated signal.

9. A method of supervising a failure of a system using a timer, comprising the steps of:

(a) counting down said timer in the case where the activated timer is not reset;

(b) executing the steps for recovering from the failure in the case where said timer goes out at a predetermined time; and

(c) in the case where said system fails to recover from the failure, repeatedly executing the steps (a) and (b) for the next timer thereby to recover from the failure in accordance with the degree of the failure progressively in each stage.