Logic level shifting circuit

• US 20020118040A1
• Filed: 02/12/2002
• Published: 08/29/2002
• Est. Priority Date: 02/28/2001
• Status: Abandoned Application

• Current Assignee: Nokia Corporation
• Original Assignee: Nokia Corporation
• Inventors: Salminen, Vesa-Matti
• Application Number:
  US10/074,079
• Publication Number:
  US 20020118040A1
• Time in Patent Office: Days
• US Class Current: 326/81
• CPC Class Codes: H03K 19/018521 of complementary type, e.g. CMOS

Abstract

A level shifting circuit (500) is provided for shifting a first voltage level to a second voltage level. The level shift is done by two inverters (542, 543) connected in cascade. The input of the first inverter forms the input port (501) of the level shifting circuit (500) where the first voltage level is input. The output of the second inverter forms the output port (502) of the level shifting circuit (500) where the second voltage level is output. The level shifting circuit (500) is operated by a single operating voltage (V_DD). It further comprises a leakage current limiting circuit (541) connected in series between the first inverter (542) and the operating voltage (V_DD) to limit a leakage current through the logic level shifting circuit (500). The level shifting circuit (500) is particularly suited to use in shifting logical 1 levels in mobile telephones.

Claims

1. A level shifting circuit for shifting a first voltage level to a second voltage level comprising an input port for inputting the first voltage level, an output port for outputting the second voltage level, a first inverter having an input and an output, a second inverter having an input and an output, the output of the first inverter being connected to the input of the second inverter, the input of the first inverter forming the input port and the output of the second inverter forming the output port, a voltage supply point via which the level shifting circuit is supplied with an operating voltage, and a leakage current limiting circuit connected in series between the first inverter and the voltage supply point for limiting a leakage current through the logic level shifting circuit.

2. A level shifting circuit according to claim 1, wherein the first voltage level is corresponding to a first logical 1 in a first digital circuit and the second voltage level is corresponding to a second logical 1 in a second digital circuit.

3. A level shifting circuit according to claim 1, wherein the second voltage level corresponds to the operating voltage.

4. A level shifting circuit according to claim 1, wherein at least one of the first inverter and the second inverter is implemented using CMOS technology.

5. A level shifting circuit according to claim 1, wherein at least one of the first inverter and the second inverter comprises a PMOS transistor and an NMOS transistor, the gate of the PMOS transistor being connected to the gate of the NMOS transistor forming the input of the inverter and the drain of the PMOS transistor being connected to the drain of the NMOS transistor forming the output of the inverter.

6. A level shifting circuit according to claim 1, wherein the leakage current limiting circuit comprises a PMOS transistor the drain of the PMOS transistor being connected to the first inverter, the source of the PMOS transistor being connected to the operating voltage, the gate of the PMOS transistor being connected to the output of the level shifting circuit and a resistor being connected between the drain of the PMOS transistor and the source of the PMOS transistor to allow a limited current flow from the operating voltage to the first CMOS inverter in a situation when the channel of the PMOS transistor is shut.

7. A level shifting circuit according to claim 6, wherein the resistor value is set so as not substantially to slow down the function of the level shifting circuit.

8. A level shifting circuit according to claim 6 wherein the resistor has a value in a range between 100 kΩ

and 1 MΩ

.

9. A digital logic circuitry comprising a plurality of subcircuits, each subcircuit using one of a plurality of voltage levels, a first voltage level of the plurality of voltage levels differing from a second voltage level of the plurality of voltage levels, a first subcircuit of the plurality of subcircuits being a level shifting circuit for shifting the first voltage level output from a second subcircuit of the plurality of subcircuits to the second voltage level for inputting to a third subcircuit of the plurality of subcircuits, the first subcircuit comprising an input port for inputting the first voltage level, an output port for outputting the second voltage level, a first inverter having an input and an output, a second inverter having an input and an output, the output of the first inverter being connected to the input of the second inverter, the input of the first inverter forming the input port and the output of the second inverter forming the output port, a voltage supply point via which the first subcircuit is supplied with an operating voltage, and a leakage current limiting circuit connected in series between the first inverter and the voltage supply point for limiting a leakage current through the first subcircuit.

10. A digital logic circuitry according to claim 9, wherein the first voltage level is corresponding to a first logical 1 in the second subcircuit and the second voltage level is corresponding to a second logical 1 in the third subcircuit.

11. A digital logic circuitry according to claim 9, wherein the second voltage level corresponds to the operating voltage.

12. A digital logic circuitry according to claim 9, wherein at least one of the first inverter and the second inverter is implemented using CMOS technology.

13. A digital logic circuitry according to claim 9, wherein at least one of the first inverter and the second inverter comprises a PMOS transistor and an NMOS transistor, the gate of the PMOS transistor being connected to the gate of the NMOS transistor forming the input of the inverter and the drain of the PMOS transistor being connected to the drain of the NMOS transistor forming the output of the inverter.

14. A digital logic circuitry according to claim 9, wherein the leakage current limiting circuit comprises a PMOS transistor the drain of the PMOS transistor being connected to the first inverter, the source of the PMOS transistor being connected to the operating voltage, the gate of the PMOS transistor being connected to the output of the second subcircuit and a resistor being connected between the drain of the PMOS transistor and the source of the PMOS transistor to allow a limited current flow from the operating voltage to the first inverter in a situation when the channel of the PMOS transistor is shut.

15. A digital logic circuitry according to claim 14, wherein the resistor value is set so as not substantially to slow down the function of the logic level shifting circuit.

16. A digital logic circuitry according to claim 14, wherein the resistor has a value in a range between 100 kΩ

and 1 MΩ

.

18. A mobile phone according to claim 17, wherein the first voltage level is corresponding to a first logical 1 in a first digital circuit and the second voltage level is corresponding to a second logical 1 in a second digital circuit.

19. A mobile phone according to claim 17, wherein the second voltage level corresponds to the operating voltage.

20. A mobile phone according to claim 17, wherein at least one of the first inverter and the second inverter is implemented using CMOS technology.

21. A mobile phone according to claim 17, wherein at least one of the first inverter and the second inverter comprises a PMOS transistor and an NMOS transistor, the gate of the PMOS transistor being connected to the gate of the NMOS transistor forming the input of the inverter and the drain of the PMOS transistor being connected to the drain of the NMOS transistor forming the output of the inverter.

22. A mobile phone according to claim 17, wherein the leakage current limiting circuit comprises a PMOS transistor the drain of the PMOS transistor being connected to the first inverter, the source of the PMOS transistor being connected to the operating voltage, the gate of the PMOS transistor being connected to the output of the second subcircuit and a resistor being connected between the drain of the PMOS transistor and the source of the PMOS transistor to allow a limited current flow from the operating voltage to the first inverter in a situation when the channel of the PMOS transistor is shut.

23. A mobile phone according to claim 22, wherein the resistor value is set so as not substantially to slow down the function of the logic level shifting circuit.

24. A mobile phone according to claim 22, wherein the resistor has a value in a range between 100 kΩ

and 1 MΩ

.

17. A mobile phone comprising a level shifting circuit for shifting a first voltage level, output from a first digital circuit, to a second voltage level for inputting to a second digital circuit, the level shifting circuit comprising an input port for inputting the first voltage level, an output port for outputting the second voltage level, a first inverter having an input and an output, a second inverter having an input and an output, the output of the first inverter being connected to the input of the second inverter, the input of the first inverter forming the input port and the output of the second inverter forming the output port, a voltage supply point via which the level shifting circuit is supplied with an operating voltage, and a leakage current limiting circuit connected in series between the first inverter and the voltage supply point for limiting a leakage current through the logic level shifting circuit.