Channel codec processor configurable for multiple wireless communications standards

• US 20020119803A1
• Filed: 12/28/2001
• Published: 08/29/2002
• Est. Priority Date: 12/29/2000
• Status: Active Grant

• Current Assignee: Intel Corporation
• Original Assignee: Infineon Technologies AG
• Inventors: Bitterlich, Stefan Johannes, Holmes, David Morris
• Granted Patent: US 7,230,978 B2
• Time in Patent Office: Days
• US Class Current: 455/552.1
• CPC Class Codes: H03M 13/09 Error detection only, e.g. using cyclic redundancy check [CRC] codes or single parity bit
• CPC Class Codes: H03M 13/29 combining two or more codes or code structures, e.g. product codes, generalised product codes, concatenated codes, inner and outer codes
• CPC Class Codes: H03M 13/2957 Turbo codes and decoding
• CPC Class Codes: H03M 13/41 using the Viterbi algorithm or Viterbi processors
• CPC Class Codes: H03M 13/6511 Support of multiple decoding rules, e.g. combined MAP and Viterbi decoding
• CPC Class Codes: H03M 13/6569 Implementation on processors, e.g. DSPs, or software implementations
• CPC Class Codes: H04L 1/0041 Arrangements at the transmitter end
• CPC Class Codes: H04L 1/0045 Arrangements at the receiver end
• CPC Class Codes: H04L 1/005 Iterative decoding, including iteration between signal detection and decoding operation
• CPC Class Codes: H04L 1/0066 Parallel concatenated codes

Abstract

A reconfigurable channel CODEC (encoder and decoder) processor for a wireless communication system is disclosed. A high degree of user programmability and reconfigurability is provided by the channel CODEC processor. In particular, the reconfigurable channel CODEC processor includes processor cores and algorithm-specific kernels that contain logic circuits tailored for carrying out predetermined but user-configurable decoding and encoding algorithms. The interconnects between the processor cores and the algorithm-specific kernels are also user-configurable. Thus, the same hardware can be reconfigured for many different wireless communication standards.

Claims

1. A channel CODEC processor, comprising:

an algorithm-specific kernel block operable to receive a data stream, the kernel block comprising logic tailored to perform at least one step of a channel CODEC algorithm on the data stream; and

a processor core coupled to provide configuration data to the algorithm-specific kernel block, the configuration data causing the kernel block to perform the at least one step of the channel CODEC algorithm according to one of a plurality of wireless communication standards as specified by the configuration data.

2. The channel CODEC processor of claim 1, further comprising an interconnect through which data flows between the processor core and the algorithm-specific kernel block, wherein the processor core is operable to provide configuration data to the interconnect to control data-flow between the processor core and the algorithm-specific kernel block.

3. The channel CODEC processor of claim 1, wherein the configuration data controls operation parameters of the algorithm-specific kernel block.

4. The channel CODEC processor of claim 1, wherein the processor core is operable to perform time-multiplexed operations for a plurality of concurrent channel CODEC tasks.

5. The channel CODEC processor of claim 1, wherein the processor core is operable to perform another step of the channel CODEC algorithm.

6. The channel CODEC processor of claim 1, wherein the processor core is operable to perform steps of another channel CODEC algorithm.

7. The channel CODEC processor of claim 1, further comprising a local memory coupled to the processor core.

8. The channel CODEC processor of claim 1, further comprising a local memory coupled to the algorithm-specific kernel block.

9. The channel CODEC processor of claim 1, wherein the logic of the algorithm-specific kernel block is tailored to decode data in the data stream according to a Viterbi decoding algorithm.

10. The channel CODEC processor of claim 1, wherein the logic of the algorithm-specific kernel block is tailored to decode data in the data stream according to a convolutional decoding algorithm.

11. The channel CODEC processor of claim 1, wherein the logic of the algorithm-specific kernel block is tailored to decode data in the data stream according to a Turbo decoding algorithm.

12. The channel CODEC processor of claim 1, wherein the algorithm-specific kernel block comprises a reconfigurable encoder for convolutional codes in which at least one polynomial parameter of the encoder is controlled by the configuration data.

13. The channel CODEC processor of claim 1, wherein the algorithm-specific kernel block comprises a reconfigurable encoder for Turbo codes in which at least one polynomial parameter of the encoder is controlled by the configuration data.

14. The channel CODEC processor of claim 1, wherein the algorithm-specific kernel block comprises a reconfigurable cyclic-redundancy check (CRC) encoder.

15. The channel CODEC processor of claim 1, wherein the algorithm-specific kernel block comprises a reconfigurable cyclic-redundancy check (CRC) checker.

17. The channel CODEC processor of claim 16, further comprising an interconnect through which data flows among the processor core and the algorithm-specific kernel blocks, wherein the processor core is operable to provide configuration data to the interconnect to control data-flow among the processor core and the algorithm-specific kernel blocks.

18. The channel CODEC processor of claim 16, wherein the first configuration data controls operation parameters of the first algorithm-specific kernel block and wherein the second configuration data controls operation parameters of the second algorithm-specific kernel block.

19. The channel CODEC processor of claim 16, wherein the processor core is operable to perform time-multiplexed operations for a plurality of concurrent channel CODEC tasks.

20. The channel CODEC processor of claim 16, wherein the processor core is operable to perform steps of the first channel CODEC algorithm and the second channel CODEC algorithm.

21. The channel CODEC processor of claim 16, wherein the processor core is operable to perform steps of a third channel CODEC algorithm.

16. A channel CODEC processor, comprising:

a first algorithm-specific kernel block operable to receive a data stream, the first algorithm-specific kernel block comprising logic tailored to perform a step of a first channel CODEC algorithm on the data stream to generate a first processed data stream;

a second algorithm-specific kernel block coupled to the first algorithm-specific kernel block to receive the first processed data stream, the second algorithm-specific kernel block comprising logic tailored to perform a step of a second channel CODEC algorithm on the first processed data stream to generate a second processed data stream; and

a processor core coupled to provide configuration data to the algorithm-specific kernel blocks, the configuration data causing the algorithm-specific kernel blocks to perform the step of the first channel CODEC algorithm and the step of the second channel CODEC algorithm according to one of a plurality of wireless communication standards as specified by the configuration data.

22. A channel CODEC processor, comprising:

an input operable to receive a data stream;

a plurality of processor cores including a first processor core and a second processor core operable to process data in the data stream;

a plurality of algorithm-specific kernel blocks including a first algorithm-specific kernel block and a second algorithm-specific kernel block coupled to the first processor core and the second processor core, respectively, wherein the first algorithm-specific kernel block is operable to receive first data from the first processor core and to perform at least one step of a first channel CODEC algorithm on the first data, wherein the second algorithm-specific kernel block is operable to receive second data from the second processor core and to perform at least one step of a second channel CODEC algorithm on the second data.

23. The channel CODEC processor of claim 22 wherein operation parameters of the first algorithm-specific kernel block and the second algorithm-specific kernel block are user-configurable.

24. The channel CODEC processor of claim 22 wherein at least one of the processor cores is coupled to provide configuration data to the algorithm-specific kernel blocks, the configuration data causing the algorithm-specific kernel blocks to perform the step of the first channel CODEC algorithm and the step of the second channel CODEC algorithm according to one of a plurality of wireless communication standards as specified by the configuration data.

25. The channel CODEC processor of claim 22, further comprising an interconnect through which data flows among the processor cores and the algorithm-specific kernel blocks, wherein at least one of the processor cores is operable to provide configuration data to the interconnect to control data-flow between the processor cores and the algorithm-specific kernel blocks.

26. The channel CODEC processor of claim 22, wherein the processor cores are operable to perform time-multiplexed operations for a plurality of concurrent channel CODEC tasks.

27. The channel CODEC processor of claim 22, further comprising memories coupled to the processor cores.

28. The channel CODEC processor of claim 22, further comprising memories coupled to the algorithm-specific kernel blocks.

30. The channel CODEC processor of claim 29, wherein the first processor core is operable to perform steps of the channel decoding algorithm.

31. The communication device of claim 29, further comprising a network interface operable to receive a data stream from a network, and wherein the channel CODEC processor further comprises:

a second algorithm-specific kernel block operable to receive the data stream, the kernel block comprising logic tailored to perform at least one step of a channel encoding algorithm on the data stream;

a second processor core coupled to provide second configuration data to the algorithm-specific kernel block, the configuration data causing the kernel block to perform the at least one step of the channel encoding algorithm according to one of a plurality of wireless communication standards as specified by the second configuration data.

32. The communication device of claim 31, wherein the second processor core is operable to perform steps of the channel decoding algorithm.

29. A communication device, comprising:

an I/O interface operable to couple to an antenna;

a modem device for modulating and demodulating data coupled to the I/O interface; and

a channel CODEC processor coupled to the modem device to receive a demodulated data stream, the channel CODEC processor comprising;

a first algorithm-specific kernel block operable to receive the demodulated data stream, the kernel block comprising logic tailored to perform at least one step of a channel decoding algorithm on the demodulated data stream; and

a first processor core coupled to provide first configuration data to the algorithm-specific kernel block, the configuration data causing the kernel block to perform the at least one step of the channel decoding algorithm according to one of a plurality of wireless communication standards as specified by the first configuration data.

33. A communication device, comprising:

an I/O interface operable to couple to an antenna;

a modem device for modulating and demodulating data coupled to the I/O interface; and

a channel CODEC processor coupled to the modem device to receive a demodulated data stream, the channel CODEC processor comprising;

a first algorithm-specific kernel block operable to receive the demodulated data stream, the first algorithm-specific kernel block comprising logic tailored to perform a step of a first channel decoding algorithm on the demodulated data stream to generate a first processed data stream;

a second algorithm-specific kernel block coupled to the first algorithm-specific kernel block to receive the first processed data stream, the second algorithm-specific kernel block comprising logic tailored to perform a step of a second channel decoding algorithm on the first processed data stream to generate a second processed data stream; and

a first processor core coupled to provide first configuration data to the algorithm-specific kernel blocks, the configuration data causing the algorithm-specific kernel blocks to perform the step of the first channel decoding algorithm and the step of the second channel decoding algorithm according to one of a plurality of wireless communication standards as specified by the first configuration data.

34. The communication device of claim 33, wherein the first processor core is operable to perform steps of the channel decoding algorithms.

35. The communication device of claim 33, further comprising a network interface operable to receive a data stream from a network.

36. The communication device of claim 35, wherein the channel CODEC processor further comprises:

a third algorithm-specific kernel block operable to receive the data stream from the network interface, the third algorithm-specific kernel block comprising logic tailored to perform a step of a first channel encoding algorithm on the data stream to generate a third processed data stream;

a fourth algorithm-specific kernel block coupled to the third algorithm-specific kernel block to receive the third processed data stream, the fourth algorithm-specific kernel block comprising logic tailored to perform a step of a second channel encoding algorithm on the first processed data stream to generate a fourth processed data stream; and

a first processor core coupled to provide second configuration data to the algorithm-specific kernel blocks, the configuration data causing the algorithm-specific kernel blocks to perform the step of the first channel encoding algorithm and the step of the second channel encoding algorithm according to one of a plurality of wireless communication standards as specified by the second configuration data.

37. The communication device of claim 36, wherein the second processor core is operable to perform steps of the channel encoding algorithms.