Controller having internal durability test cycle driver

• US 20020120421A1
• Filed: 07/16/2001
• Published: 08/29/2002
• Est. Priority Date: 02/27/2001
• Status: Abandoned Application

• Current Assignee: Delphi Technologies, Inc. (Aptiv PLC)
• Original Assignee: Delphi Technologies, Inc. (Aptiv PLC)
• Inventors: Carsey, Joyce D., Crawford, Daniel A.
• Application Number:
  US09/906,315
• Publication Number:
  US 20020120421A1
• Time in Patent Office: Days
• US Class Current: 702/122
• CPC Class Codes: G05B 23/0256 injecting test signals and analyzing monitored process response, e.g. injecting the test signal while interrupting the normal operation of the monitored system; superimposing the test signal onto a control signal during normal operation of the monitored system

Abstract

An exemplary embodiment of the invention is an actuator assembly having a controller integrated into the actuator assembly. The controller includes a memory for storing test cycle data and a processor in communication with the memory. The processor accesses the test cycle data. A communication port is in communication with the processor and in communication with an actuator and a sensor. During a test mode, the processor provides position commands to the actuator and receives a sensor signal from the sensor. The processor detects the presence of faults in response to the sensor signal and stores the faults in the memory.

Claims

1. An actuator assembly comprising:

a controller integrated into said actuator assembly, said controller including;

memory storing test cycle data;

a processor in communication with said memory, said processor accessing said test cycle data;

a communication port in communication with said processor and in communication with an actuator and a sensor;

wherein during a test mode, said processor provides position commands to said actuator and receives a sensor signal from said sensor,

said processor detecting faults in response to said sensor signal and storing faults in said memory.

2. The actuator assembly of claim 1, wherein said memory comprises non-volatile random access memory.

3. The actuator assembly of claim 1, wherein said test cycle data defines a commanded actuator position and said sensor signal provides a measured actuator position, said faults being indicative of a difference between said commanded actuator position and said measured actuator position.

4. The actuator assembly of claim 1, wherein said test cycle data includes command position data and time data.

5. The actuator assembly of claim 1, wherein said communication port is in communication with said sensor and said actuator over a controller area network.

6. The actuator assembly of claim 1, further comprising a communications device for communicating with a master controller.

7. The actuator assembly of claim 6, wherein said communications device is a universal asynchronous receiver/transmitter.

8. The actuator assembly of claim 1, wherein said memory includes a test profile byte and a redundant test profile byte, said processor confirming validity of the test profile byte and the redundant test profile byte prior to initiating said test mode.

9. The actuator assembly of claim 1, wherein said processor includes a test input pin, said processor confirming a state of said test input pin prior to initiating said test mode.

10. The actuator assembly of claim 1, wherein said memory includes a test enable bit, said processor confirming a state of said test enable bit prior to initiating said test mode.

11. The actuator assembly of claim 1, wherein said memory includes a test profile byte and a redundant test profile byte, said processor confirming validity of the test profile byte and the redundant test profile byte prior to initiating said test mode;

wherein said processor includes a test input pin, said processor confirming a state of said test input pin prior to initiating said test mode; and

,

wherein said memory includes a test enable bit, said processor confirming a state of said test enable bit prior to initiating said test mode.