Network co-processor for vehicles

• US 20020120888A1
• Filed: 02/14/2002
• Published: 08/29/2002
• Est. Priority Date: 02/14/2001
• Status: Active Grant

• Current Assignee: Micronas Gmbh (TDK Corporation)
• Original Assignee: Micronas Gmbh (TDK Corporation)
• Inventors: Franke, Jorg
• Granted Patent: US 7,260,668 B2
• Time in Patent Office: Days
• US Class Current: 714/42
• CPC Class Codes: G06F 15/78 comprising a single central processing unit

Abstract

A network processor (1) exchanges data of various descriptions via a plurality of network nodes (10) with external network devices, such as other processors, controllers, transducers, or sensors. The network processor includes a master processor (13) for control tasks of the processor, and a network coprocessor (40) for supporting network tasks. A first and a second bus system (30, 35), associated essentially with the master processor (13) and the network coprocessor (40) with its associated functional units, particularly Data Link Layer memory devices (20), respectively, serves to separate the two fields of tasks from each other. This permits both a support of gateway functions and a support of Higher Layer functions. Higher Layer memory devices (21), whose messages are ultimately sent or received by the master processor (13), are accessible from the master processor (13) or the network coprocessor (40) directly or indirectly via the first and/or second bus systems (30, 35).

Claims

1. A network processor (1), comprising:

a master processor (13) and a network coprocessor (4) which is coupled to network nodes;

a first bus system (30), associated essentially with the master processor (13) and also serving to couple the network coprocessor (40) to the master processor(13);

a second bus system (35), associated essentially with the network coprocessor and also serving to couple the individual network nodes (10) to the network coprocessor;

a first network memory (20), having an area for first layer messages (DLL) which is associated with the second bus system (35) and which contains the messages to be read or written for the associated network nodes (10);

a second network memory (21), having an area for second layer messages (HL) which contains the information serving to convert the first layer messages to be read or written, said second network memory (21) being associated either

with the first system (30), in which case a first direct memory access device (50) between the second and first bus systems (35, 30) permits direct and, thus, rapid access by the network coprocessor (40) to the second network memory (21),

or

with the second bus system (35), in which case a second direct memory access device (50.1) between the first and second bus systems (30, 35) permits direct and, thus, rapid access by the master processor to the second network memory.

2. A network processor (1) as set forth in claim 1, characterized in that the second direct memory access device (50.1) is replaced by a two-port design of the second network memory (21.1), with the first port connected to the first bus system (30) and the second port connected to the second bus system (35).

3. A network processor (1) as set forth in claim 2, characterized in that at least some of the network nodes (10) each have a separate memory area (10.7, 10.8, 10.9) which replaces the associated area of the first network memory (20) in whole or in part.

4. A network processor (1) as set forth in claim 2, characterized in that a third bus system (60) is provided, to which the network nodes (10) and a first input/output of the first network memory (20) are connected, the second input/output of the network memory (20) being connected to the second bus system (35).

5. A network processor (1) as set forth in claim 4, characterized in that a priority logic (55) connected to the third bus system (60) provides contention control in the event of simultaneous access by more than one network node (10) to the third bus system (60).