MIXED ANALOG AND DIGITAL INTEGRATED CIRCUITS

• US 20020121679A1
• Filed: 03/02/2001
• Published: 09/05/2002
• Est. Priority Date: 03/02/2001
• Status: Active Grant

• Current Assignee: Qualcomm, Inc.
• Original Assignee: Qualcomm, Inc.
• Inventors: Zou, Qiuzhen, Zhang, Haitao, Bazarjani, Seyfollah, Jha, Sanjay
• Granted Patent: US 6,472,747 B2
• Time in Patent Office: Days
• US Class Current: 257/666
• CPC Class Codes: G01R 31/2853 Electrical testing of internal connections or -isolation, e.g. latch-up or chip-to-lead connections G01R31/31717 takes precedence; test of chip-to-PCB or lead-to-PCB connections G01R31/66
• CPC Class Codes: H01L 2224/05554 being square
• CPC Class Codes: H01L 2224/05599 Material
• CPC Class Codes: H01L 2224/06164 covering only portions of the surface to be connected
• CPC Class Codes: H01L 2224/06165 Covering only the peripheral area of the surface to be connected, i.e. peripheral arrangements
• CPC Class Codes: H01L 2224/32145 the bodies being stacked
• CPC Class Codes: H01L 2224/32225 the item being non-metallic, e.g. insulating substrate with or without metallisation
• CPC Class Codes: H01L 2224/45015 being circular
• CPC Class Codes: H01L 2224/45099 Material
• CPC Class Codes: H01L 2224/48145 the bodies being stacked
• CPC Class Codes: H01L 2224/48227 connecting the wire to a bond pad of the item
• CPC Class Codes: H01L 2224/49171 Fan-out arrangements
• CPC Class Codes: H01L 2224/49175 Parallel arrangements
• CPC Class Codes: H01L 2224/73265 Layer and wire connectors
• CPC Class Codes: H01L 2224/85399 Material
• CPC Class Codes: H01L 2225/06506 Wire or wire-like electrical connections between devices
• CPC Class Codes: H01L 2225/0651 Wire or wire-like electrical connections from device to substrate
• CPC Class Codes: H01L 2225/06582 Housing for the assembly, e.g. chip scale package [CSP]
• CPC Class Codes: H01L 23/3128 the substrate having spherical bumps for external connection
• CPC Class Codes: H01L 24/48 of an individual wire connector
• CPC Class Codes: H01L 24/49 : of a plurality of wire connectors
• CPC Class Codes: H01L 24/73 : Means for bonding being of different types provided for in two or more of groups H01L24/10, H01L24/18, H01L24/26, H01L24/34, H01L24/42, H01L24/50, H01L24/63, H01L24/71
• CPC Class Codes: H01L 25/0657 : Stacked arrangements of devices
• CPC Class Codes: H01L 25/18 : the devices being of types provided for in two or more different subgroups of the same main group of groups H01L27/00 - H01L33/00, or in a single subclass of H10K, H10N
• CPC Class Codes: H01L 2924/00 : Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
• CPC Class Codes: H01L 2924/00012 : Relevant to the scope of the group, the symbol of which is combined with the symbol of this group
• CPC Class Codes: H01L 2924/00014 : the subject-matter covered by the group, the symbol of which is combined with the symbol of this group, being disclosed without further technical details
• CPC Class Codes: H01L 2924/14 : Integrated circuits
• CPC Class Codes: H01L 2924/141 : Analog devices
• CPC Class Codes: H01L 2924/143 : Digital devices
• CPC Class Codes: H01L 2924/1435 : Random access memory [RAM]
• CPC Class Codes: H01L 2924/145 : Read-only memory [ROM]
• CPC Class Codes: H01L 2924/15311 : being a ball array, e.g. BGA
• CPC Class Codes: H01L 2924/19041 : being a capacitor
• CPC Class Codes: H01L 2924/207 : Diameter ranges

Abstract

Techniques for fabricating analog and digital circuits on separate dies and stacking and integrating the dies within a single package to form a mixed-signal IC that provides many benefits. In one aspect, the analog and digital circuits are implemented on two separate dies using possibly different IC processes suitable for these different types of circuits. The analog and digital dies are thereafter integrated (stacked) and encapsulated within the single package. Bonding pads are provided to interconnect the dies and to connect the dies to external pins. The bonding pads may be located and arranged in a manner to provide the required connectivity while minimizing the amount of die area required to implement the pads. In another aspect, the die-to-die connectivity may be tested in conjunction with a serial bus interface.

Claims

1. A mixed-signal integrated circuit comprising:

a package substrate having a plurality of bonding pads;

a first die having a plurality of bonding pads and placed on a top surface of the package substrate, wherein predominantly digital circuits are fabricated on the first die; and

a second die having a plurality of bonding pads and placed on a top surface of the first die, wherein predominantly analog circuits are fabricated on the second die.

2. The integrated circuit of claim 1, wherein the plurality of bonding pads for each of the first and second dies are located near edges of the die.

3. The integrated circuit of claim 1, wherein the first die comprises

a first set of bonding pads for interconnection with associated bonding pads on the second die, and

a second set of bonding pads for interconnection with associated bonding pads on the package substrate.

4. The integrated circuit of claim 3, wherein the bonding pads in the first and second sets are inter-digitized.

5. The integrated circuit of claim 3, wherein the bonding pads in the first and second sets are alternatively arranged along a line.

6. The integrated circuit of claim 1, wherein the first die includes a set of bonding pads located away from the edges of the first die.

7. The integrated circuit of claim 1, wherein the package substrate and first and second dies are encapsulated within a single package.

8. The integrated circuit of claim 1, wherein the package substrate and first and second dies are dimensioned to have a profile that conforms to specifications for a standard package.

9. The integrated circuit of claim 8, wherein the standard package is a ball grid array.

10. The integrated circuit of claim 1, wherein each of the first and second dies is derived from a wafer that has been processed to achieve a particular thickness.

11. The integrated circuit of claim 10, wherein the particular thickness is obtained by back grinding the wafer.

12. The integrated circuit of claim 1, wherein the first and second dies are fabricated using two different integrated circuit (IC) process technologies.

13. The integrated circuit of claim 1, wherein the first die is fabricated using a CMOS process technology.

16. The integrated circuit of claim 15, wherein the voltages for the selected ones of the supply signals are collapsed to zero during the stand-by operating mode.

17. The integrated circuit of claim 15, wherein the control unit is maintained powered on during the stand-by operating mode.

19. The method of claim 18, further comprising:

sending a second test value from the second die via the interconnection wire to the first die;

detecting the second test value on the first die;

providing the detected second test value as a second control value on the serial bus interface; and

comparing the second control value with the second test value to verify connectivity of the interconnection wire.

14. A mixed-signal integrated circuit comprising:

a package substrate having a plurality of bonding pads;

a first die having a plurality of bonding pads and placed on top of the package substrate, wherein predominantly digital circuits are fabricated on the first die;

a second die having a plurality of bonding pads and placed on top of a portion of the first die, wherein predominantly analog circuits are fabricated on the second die; and

a package encapsulating the package substrate and the first and second dies, and

wherein the first and second dies are fabricated using two different integrated circuit (IC) process technologies.

15. A mixed-signal integrated circuit comprising:

a first die having predominantly digital circuits fabricated thereon; and

a second die having predominantly analog circuits fabricated thereon, the second die further including a control unit coupled to an interface and one or more pads for receiving one or more supply signals for the analog circuits, wherein the control unit is configured to control operating modes of selected ones of the analog circuits on the second die, and wherein voltages for selected ones of the supply signals are reduced during a stand-by operating mode.

18. A method for testing an interface between first and second dies encapsulated within a single package, the method comprising:

providing a first control value to a serial bus interface, wherein the first control value directs a first test value to be sent from the first die to the second die;

sending the first test value from the first die to the second die via an interconnection wire in response to the first control value;

receiving the first test value on the second die; and

comparing the first control value with the received first test value to verify connectivity of the interconnection wire.