Automated pattern clustering detection for wafer probe maps

• US 20020121915A1
• Filed: 03/05/2001
• Published: 09/05/2002
• Est. Priority Date: 03/05/2001
• Status: Abandoned Application

• Current Assignee: Agere Systems Guardian Corp. (Broadcom, Inc.)
• Original Assignee: Agere Systems Guardian Corp. (Broadcom, Inc.)
• Inventors: Ortega, Carlos, Villen Pizarro, Julia Maria, Alonso Montull, Juan Ignacio, Sobrino Patino, Eliseo Ventura
• Application Number:
  US09/799,337
• Publication Number:
  US 20020121915A1
• Time in Patent Office: Days
• US Class Current: 324/765
• CPC Class Codes: H01L 21/67288 Monitoring of warpage, curvature, damage, defects or the like
• CPC Class Codes: H01L 22/20 Sequence of activities consisting of a plurality of measurements, corrections, marking or sorting steps

Abstract

A method for characterizing defects of integrated circuits on a semiconductor wafer includes storing at least one reference wafer map in a memory corresponding to a known defect pattern of the integrated circuits caused during a manufacturing step thereof, testing the integrated circuits for defects, generating a test wafer map for the semiconductor wafer comprising a pattern of each defective integrated circuit thereon, comparing the test wafer map to the at least one reference wafer map to determine if the known defect pattern is present in the test wafer map, and generating a new reference wafer map corresponding to the test wafer map if the test wafer map has an unknown defect pattern. An apparatus for characterizing defects of integrated circuit die on a semiconductor wafer is also provided.

Claims

1. A method for characterizing defects of integrated circuit die on a semiconductor wafer comprising:

storing at least one reference wafer map in a memory corresponding to a known defect pattern of the integrated circuits caused during a manufacturing step thereof;

testing the integrated circuit die on the semiwafer for defective integrated circuit die;

generating a test wafer map for the semiconductor wafer comprising a pattern of each defective integrated circuit die thereon;

comparing the test wafer map to the at least one reference wafer map to determine if the known defect pattern is present in the test wafer map; and

generating a new reference wafer map corresponding to the test wafer map if the test wafer map has an unknown defect pattern.

2. The method of claim 1 wherein the semiconductor wafer comprises a plurality of semiconductor wafers;

and further comprising grouping test wafer maps having at least one common defect pattern.

3. The method of claim 2 further comprising generating a report indicating a frequency of test wafer maps having the at least one common defect pattern.

4. The method of claim 1 further comprising subjecting the test wafer pattern to a statistical smoothing operation to delete random defects.

5. The method of claim 1 wherein the at least one reference wafer map comprises a plurality of reference wafer maps and the semiconductor wafer comprises a plurality of semiconductor wafers;

and further comprising grouping the plurality of reference wafer maps and the plurality of test wafer maps to provide a reference wafer lot.

6. The method of claim 1 further comprising storing the new reference wafer map in the memory.

7. A method for characterizing defects of integrated circuit die on a plurality of semiconductor wafers comprising:

storing a plurality of reference wafer maps in a memory each corresponding to a known defect pattern of the integrated circuits caused during a manufacturing step thereof;

testing the integrated circuit die on each semiconductor wafer for defective integrated circuit die;

generating a test wafer map for each semiconductor wafer comprising a pattern of each defective integrated circuit thereon;

comparing each of the test wafer maps to the plurality of reference wafer maps to determine if at least one known defect pattern is present in the test wafer map;

generating a new reference wafer map corresponding to each generated test wafer map having an unknown defect pattern; and

storing the new reference wafer map in the memory.

8. The method of claim 7 further comprising grouping test wafer maps having the at least one common defect pattern.

9. The method of claim 8 further comprising generating a report indicating a frequency of test wafer maps having the at least one common defect pattern.

10. The method of claim 7 further comprising subjecting each test wafer pattern to a statistical smoothing operation to delete random defects.

11. The method of claim 7 further comprising grouping the plurality of reference wafer maps and the plurality of test wafer maps to provide a reference wafer lot.

13. The apparatus of claim 12 wherein the semiconductor wafer comprises a plurality of semiconductor wafers;

and wherein said processor groups test wafer maps having at least one common defect pattern.

14. The apparatus of claim 13 wherein said processor generates a report indicating a frequency of test wafer maps having the at least one common defect pattern.

15. The apparatus of claim 12 wherein said processor performs a statistical smoothing operation on the test wafer pattern to delete random defects.

16. The apparatus of claim 12 wherein the at least one reference wafer map comprises a plurality of reference wafer maps and the wafer comprises a plurality of wafers;

and wherein said processor groups the plurality of reference wafer maps and the plurality of test wafer maps to provide a reference wafer lot.

17. The apparatus of claim 12 wherein said processor causes the new reference wafer map to be stored in said memory.

12. An apparatus for characterizing defects of integrated circuit die on a semiconductor wafer comprising:

a test probe for testing the integrated circuit die for defects;

a memory for storing at least one reference wafer map corresponding to a known defect pattern of the integrated circuit die caused during a manufacturing step thereof; and

a processor connected to said test probe and said memory, said processor

generating a test wafer map for the semiconductor wafer comprising a pattern of each defective integrated circuit die thereon,

comparing the test wafer map to the at least one reference wafer map to determine if the known defect pattern is present in the test wafer map, and

generating a new reference wafer map corresponding to the test wafer map if the test wafer map has an unknown defect pattern.