METHOD AND APPARATUS FOR DRIVING LIQUID CRYSTAL DISPLAY PANEL

• US 20020122041A1
• Filed: 02/16/1999
• Published: 09/05/2002
• Est. Priority Date: 03/18/1998
• Status: Active Grant

• Current Assignee: Sharp Kabushiki Kaisha (Hon Hai Precision Industry Co., Ltd.)
• Original Assignee: Fujitsu Display Technologies Corporation (Fujitsu Limited)
• Inventors: KAI, TSUTOMU, KANEKO, YOSHIYA
• Granted Patent: US 6,753,841 B2
• Time in Patent Office: Days
• US Class Current: 345/581
• CPC Class Codes: G09G 2340/0414 Vertical resolution change
• CPC Class Codes: G09G 3/3648 using an active matrix G09G3/367 - G09G3/3696 take precedence
• CPC Class Codes: G09G 3/3677 suitable for active matrices only
• CPC Class Codes: G09G 3/3688 suitable for active matrices only
• CPC Class Codes: G09G 5/005 Adapting incoming signals to the display format of the display terminal
• CPC Class Codes: G09G 5/006 Details of the interface to the display terminal specific for a display terminal using a CRT G09G1/167; using a flat panel G09G3/2096; circuits for interfacing with colour displays G09G5/04

Abstract

A LCD apparatus has a control circuit 40 which makes a timing of the rear edge of scanning pulses provided to predetermined scanning lines coincide with the time when the display potential is renewed, wherein each of the predetermined scanning lines corresponds to an addition of picture line to a picture or a reduction from two picture lines to one picture line on a picture in order to compensate a difference between the number of scanning lines of the LCD and that of lines of the picture to be displayed. In the control circuit 40, a circuit 45 detects cycle times of the vertical and horizontal sync pulses, a MPU 46 determines the reference value REF on the basis of the detected value and count CH of the horizontal sync pulse *HS from a counter 44, and a circuit 47 generates a signal AE which makes the time when the pulse count CD of pixel clock CLKD from the counter 42 becomes equal to the REF coincide with the timing of the rear edge of scanning pulse.

Claims

1. A liquid crystal display apparatus, comprising:

an active matrix type liquid crystal panel in which potentials of respective data lines are applied to respective display electrodes of a selected display line via respective switching devices of said selected display line, said selected display line corresponding to a selected one of scanning lines;

a data driver for applying said potentials to said respective data lines and renewing said potentials at every horizontal cycle;

a scanning driver for providing scanning pulses to said respective scanning lines in line-sequence; and

a control circuit for causing a timing of the rear edge of a scanning pulse provided to a predetermined scanning line to coincide with a time when said potentials of said data lines is renewed,

wherein said predetermined scanning line is one corresponding to an addition of picture line to or a reduction of picture line from a picture to be displayed, in order to compensate a difference between the number of said scanning lines and that of picture lines of said picture to be displayed.

2. A liquid crystal display apparatus according to claim 1, wherein said control circuit comprises:

a first counter counting pulses of a clock signal and initialized by a horizontal synchronization pulse; and

a pulse rear edge timing circuit for setting said timing of said rear edge at a time when a count of said first counter is equal to a first value.

3. A liquid crystal display apparatus according to claim 2, wherein said clock signal is a pixel clock signal.

4. A liquid crystal display apparatus according to claim 2, wherein said control circuit further comprises:

a second counter counting said horizontal synchronization pulses and initialized by a vertical synchronization pulse; and

wherein said pulse rear edge timing circuit executes said setting when a count of said second counter is equal to a second value.

5. A liquid crystal display apparatus according to claim 4, further comprising a reference value determination circuit for detecting cycle times of said horizontal synchronization pulse and said vertical synchronization pulse and for determining said first value on the basis of the detected cycle times and a count of said second counter.

6. A liquid crystal display apparatus according to claim 2, wherein said scanning driver comprises:

a shift register in which a selection bit is shifted by one bit at every scanning pulse;

an output buffer circuit having outputs connected to respective said scanning lines; and

a timing adjustment circuit for determining an output of said output buffer circuit on the basis of a parallel output of said shift register and an output of said pulse rear edge timing circuit.

7. A liquid crystal display apparatus according to claim 6, wherein said timing adjustment circuit causes said output buffer circuit to generate said scanning pulse corresponding to a bit of said parallel output when this bit becomes said selected bit and to disappear said scanning pulse when a binary output of said pulse rear edge timing circuit becomes active.

8. A liquid crystal display apparatus according to claim 1, wherein said timing in said control circuit approximately coincides with a time point when said display potential becomes the center between the maximum and minimum display potentials in a same polarity.

9. A control circuit for use in a liquid crystal display apparatus, said control circuit causing a timing of the rear edge of a scanning pulse provided to a predetermined scanning line to coincide with a time when potentials of data lines is renewed,

wherein said predetermined scanning line is one corresponding to an addition of picture line to or a reduction of picture line from a picture to be displayed, in order to compensate a difference between the number of said scanning lines and that of picture lines of said picture to be displayed.

10. A method of driving a liquid crystal display panel, comprising the steps of:

providing an active matrix type liquid crystal panel in which potentials of respective data lines are applied to respective display electrodes of a selected display line via respective switching devices of said selected display line, said selected display line corresponding to a selected one of scanning lines;

applying said potentials to said respective data lines and renewing said potentials at every horizontal cycle;

providing scanning pulses to said respective scanning lines in line-sequence; and

causing a timing of the rear edge of a scanning pulse provided to a predetermined scanning line to coincide with a time when said potentials of said data lines is renewed,

wherein said predetermined scanning line is one corresponding to an addition of picture line to or a reduction of picture line from a picture to be displayed, in order to compensate a difference between the number of said scanning lines and that of picture lines of said picture to be displayed.

11. A method according to claim 10, wherein the step of said causing includes the steps of:

initializing a first count with a horizontal synchronization pulse and counting clock pulses to get said first count;

initializing a second count with a vertical synchronization pulse and counting said horizontal synchronization pulses to get said second count; and

setting said timing of said rear edge at a time when said first and second counts become first and second values, respectively.

12. A method according to claim 11, wherein the step of said causing further includes the steps of:

detecting cycle times of said horizontal synchronization pulse and said vertical synchronization pulse; and

determining said first value on the basis of the detected cycle times and said second count.

13. A method according to claim 11, wherein said timing in the step of said setting approximately coincides with a time point when said display potential becomes the center between the maximum and minimum display potentials in a same polarity.