Capacitor, circuit board with built-in capacitor and method for producing the same

• US 20020122283A1
• Filed: 02/27/2002
• Published: 09/05/2002
• Est. Priority Date: 03/01/2001
• Status: Active Grant

• Current Assignee: Shinko Electric Industries Company Limited (Fujitsu Limited)
• Original Assignee: Shinko Electric Industries Company Limited (Fujitsu Limited)
• Inventors: Omori, Koji, Higashi, Mitsutoshi, Mochizuki, Takashi
• Granted Patent: US 6,678,144 B2
• Time in Patent Office: Days
• US Class Current: 361/271
• CPC Class Codes: H01G 9/028 Organic semiconducting electrolytes, e.g. TCNQ
• CPC Class Codes: H01G 9/042 characterised by the material H01G11/22 takes precedence
• CPC Class Codes: H01L 23/49822 Multilayer substrates multilayer metallisation on monolayer substrate H01L23/498
• CPC Class Codes: H01L 2924/00 Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
• CPC Class Codes: H01L 2924/0002 Not covered by any one of groups H01L24/00, H01L24/00 and H01L2224/00
• CPC Class Codes: H01L 2924/09701 Low temperature co-fired ceramic [LTCC]
• CPC Class Codes: H01L 2924/12044 OLED
• CPC Class Codes: H01L 2924/3011 Impedance
• CPC Class Codes: H05K 1/162 incorporating printed capacitors
• CPC Class Codes: H05K 2201/0175 Inorganic, non-metallic layer, e.g. resist or dielectric for printed capacitor
• CPC Class Codes: H05K 2201/0179 Thin film deposited insulating layer, e.g. inorganic layer for printed capacitor
• CPC Class Codes: H05K 2201/0329 Intrinsically conductive polymer [ICP]; Semiconductive polymer
• CPC Class Codes: H05K 2201/09509 Blind vias, i.e. vias having one side closed
• CPC Class Codes: H05K 2203/0315 Oxidising metal
• CPC Class Codes: H05K 3/4602 characterized by a special circuit board as base or central core whereon additional circuit layers are built or additional circuit boards are laminated

Abstract

A capacitor is formed between a lower wiring layer and an upper wiring layer in an interior of a circuit board. The capacitor comprises a lower metallic layer consisting of at least one valve metal selected from the group consisting of aluminum, tantalum, niobium, tungsten, vanadium, bismuth, titanium, zirconium and hafnium, a dielectric layer consisting of an oxide of the valve metal which may be the same as or different from the valve metal of the lower metallic layer, an intermediate layer consisting of a solid electrolyte, and an upper metallic layer consisting of an electrode metal, laminated in this order.

Claims

1. A capacitor to be disposed between a lower wiring layer and an upper wiring layer in an interior of a circuit board, which comprises a lower metallic layer consisting of at least one valve metal selected from the group consisting of aluminum, tantalum, niobium, tungsten, vanadium, bismuth, titanium, zirconium and hafnium, a dielectric layer consisting of an oxide of the valve metal which may be the same as or different from that of the lower metallic layer, an intermediate layer consisting of a solid electrolyte, and an upper metallic layer consisting of an electrode metal, laminated in this order.

2. A capacitor as defined in claim 1, wherein the dielectric layer comprises a metal oxide formed upon anodizing of the lower metallic layer or upon forming a film with a film-forming material.

3. A capacitor as defined in claim 1 or 2, wherein the intermediate layer comprises a conductive polymer, an organic semiconductor material or a conductive metal oxide.

4. A capacitor as defined in claim 1 or 2, wherein the lower wiring layer has a topographic pattern on a surface thereof, the pattern being reproduced in the lower metallic layer and the dielectric layer formed thereon.

5. A capacitor as defined in claim 4, wherein a surface roughness of the topographic pattern in the lower metallic layer is in a range from 5 to 50 μ

m as measured in a vertical distance between a top of the projections and a bottom of the pits in the layer.

6. A circuit board with a built-in capacitor wherein a capacitor is sandwiched between a lower wiring layer and an upper wiring layer in the interior of the circuit board, the capacitor comprising a lower metallic layer consisting of at least one valve metal selected from the group consisting of aluminum, tantalum, niobium, tungsten, vanadium, bismuth, titanium, zirconium and hafnium, a dielectric layer consisting of an oxide of the valve metal which may be the same as or different from that of the lower metallic layer, an intermediate layer consisting of a solid electrolyte, and an upper metallic layer consisting of an electrode metal, are laminated in this order.

7. A circuit board as defined in claim 6, wherein the dielectric layer comprises a metal oxide formed upon an anodizing of the lower metallic layer or upon forming a film with a film-forming material.

8. A circuit board as defined in claim 6 or 7, wherein the intermediate layer comprises a conductive polymer, organic semiconductor material or conductive metal oxide.

9. A circuit board as defined in claim 6 or 7, wherein the lower wiring layer has a topographic pattern on a surface thereof, the pattern being reproduced in the lower metallic layer and in the dielectric layer formed thereon.

10. A circuit board as defined in claim 9, wherein a surface roughness of the topographic pattern in the lower metallic layer is in a range from 5 to 50 μ

m as measured over a vertical distance between a top of projections and a bottom of pits in the layer.

11. A circuit board as defined in claim 6 or 7, wherein the circuit board is a multi-layered circuit board having a built-up structure.

13. A method for producing a capacitor as defined in claim 12, wherein the dielectric layer comprises a metal oxide formed upon an anodizing of the lower metallic layer or upon forming a film with a film-forming material.

14. A method for producing a capacitor as defined in claim 12 or 13, further comprising the step of roughening a surface of the lower wiring layer after formation of the wiring layer to thereby impart a topographic pattern to the lower metallic layer and the dielectric layer sequentially formed thereon, in addition to the wiring layer.

15. A method for producing a capacitor as defined in claim 14, wherein a surface roughness of the topographic pattern in the lower metallic layer is controlled to be in a range from 5 to 50 μ

m as measured over a vertical distance between a top of projections and a bottom of pits.

17. A method for producing a circuit board as defined in claim 16, wherein the dielectric layer comprises a metal oxide formed upon anodizing of the lower metallic layer or upon forming a film with a film-forming material.

18. A method for producing a circuit board as defined in claim 16 or 17, further comprising the step of roughening a surface of the core substrate to thereby impart a topographic pattern to the lower wiring layer, the lower metallic layer and the dielectric layer sequentially formed thereon, in addition to the core substrate.

19. A method for producing a circuit board as defined in claim 16 or 17, further comprising, after formation of the lower wiring layer on the core substrate, the step of roughening a surface of the lower wiring layer to impart to a surface of the wiring layer a topographic pattern which is then reproduced in the lower metallic layer and the dielectric layer sequentially formed thereon.

20. A method for producing a circuit board as defined in claim 18 or 19, wherein a surface roughness of the topographic pattern in the lower metallic layer is controlled to be in a range from 5 to 50 μ

m as measured by a vertical distance between a top of projections and a bottom of pits.

21. A method for producing a circuit board as defined in claim 16, further comprising, after formation of the capacitor on the core substrate, the steps of forming an insulation film covering the capacitor and then forming a second capacitor on the insulation film in the same manner as in the formation of the above capacitor.

12. A method for producing a capacitor to be disposed between a lower wiring layer and an upper wiring layer, in an interior of a circuit board, which method comprises the steps of, after formation of the lower wiring layer:

forming a lower metallic layer, on the lower wiring layer, from at least one valve metal selected from the group consisting of aluminum, tantalum, niobium, tungsten, vanadium, bismuth, titanium, zirconium and hafnium;

forming a dielectric layer, on the lower metallic layer, from an oxide of the valve metal which may be the same as or different from that of the lower metallic layer;

forming an intermediate layer, on the dielectric layer, from a solid electrolyte selected from the group consisting of a conductive polymer, organic semiconductor material and conductive metallic oxide; and

forming an upper metallic layer, on the intermediate layer, from an electrode metal.

16. A method for producing a circuit board with a built-in capacitor wherein a capacitor is sandwiched between a lower wiring layer and an upper wiring layer in an interior of the circuit board, which method comprises the steps of:

after formation of the lower wiring layer consisting of a conductive metal on a core substrate;

forming a lower metallic layer, on the lower wiring layer, from at least one valve metal selected from the group consisting of aluminum, tantalum, niobium, tungsten, vanadium, bismuth, titanium, zirconium and hafnium;

forming a dielectric layer, on the lower metallic layer, from an oxide of the valve metal which may be the same as or different from that of the lower metallic layer;

forming an intermediate layer, on the dielectric layer, from a solid electrolyte selected from the group consisting of a conductive polymer, organic semiconductor material and conductive metal oxide;

forming an upper metallic layer, on the intermediate layer, from an electrode metal; and

further forming the upper wiring layer consisting of a conductive metal on the thus formed capacitor.