Multi-pair gigabit ethernet transceiver
First Claim
1. An integrated circuit communication device configured for operation over a multi-pair transmission channel, the communication device comprising:
- a decoder adapted to decode a signal having N states, and generating tentative decisions regarding a path and a final decision;
a single-state decision feedback equalizer having a set of ordered coefficients and adapted to receive the tentative decisions and to produce a single-state intersymbol interference (ISI) compensation signal corresponding to a first ISI component based on the tentative decisions and the set of ordered coefficients; and
a state multiplication circuit adapted to produce an N-state representation signal, suitable for decoding by the decoder, based on the single-state ISI compensation signal.
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Accused Products
Abstract
Various systems and methods providing high speed decoding, enhanced power reduction and clock domain partitioning for a multi-pair gigabit Ethernet transceiver are disclosed. ISI compensation is partitioned into two stages; a first stage compensates ISI components induced by characteristics of a transmitters partial response pulse shaping filter in a demodulator, a second stage compensates ISI components induced by characteristics of a multi-pair transmission channel in a Viterbi decoder. High speed decoding is accomplished by reducing the DFE depth by providing an input signal from a multiple decision feedback equalizer to the Viterbi based on a tail value and a subset of coefficient values received from a unit depth decision-feedback equalizer. Power reduction is accomplished by adaptively truncating active taps in the NEXT, FEXT and echo cancellation filters, or by disabling decoder circuitry portions, as channel response characteristics allow. A receive clock signal is generated such that it is synchronous in frequency with analog sampling clock signals and has a particular phase offset with respect to one of the sampling clock signals. This phase offset is adjusted such that system performance degradation due to coupling of switching noise from the digital sections to the analog sections is substantially minimized.
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Citations
15 Claims
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1. An integrated circuit communication device configured for operation over a multi-pair transmission channel, the communication device comprising:
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a decoder adapted to decode a signal having N states, and generating tentative decisions regarding a path and a final decision;
a single-state decision feedback equalizer having a set of ordered coefficients and adapted to receive the tentative decisions and to produce a single-state intersymbol interference (ISI) compensation signal corresponding to a first ISI component based on the tentative decisions and the set of ordered coefficients; and
a state multiplication circuit adapted to produce an N-state representation signal, suitable for decoding by the decoder, based on the single-state ISI compensation signal. - View Dependent Claims (2, 3, 4, 5, 6, 7, 8)
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9. A method of processing a communication signal having N states and transmitted over a multi-pair transmission channel, the method comprising steps of:
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(a) decoding a signal having N states;
(b) generating tentative decisions regarding a path and a final decision;
(c) producing a single-state intersymbol interference (ISI) compensation signal corresponding to a first ISI component based on the tentative decisions and a set of ordered coefficients; and
(d) producing an N-state representation signal, suitable for decoding by decoding step (a), based on the single-state ISI compensation signal. - View Dependent Claims (10, 11, 12, 13, 14, 15)
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Specification