Circuit configuration and method for directly electrically isolated broadband transmission

• US 20020122496A1
• Filed: 12/26/2001
• Published: 09/05/2002
• Est. Priority Date: 06/25/1999
• Status: Active Grant

• Current Assignee: Gigaset Communications GmbH (Gigaset AG)
• Original Assignee: Siemens AG
• Inventors: Klein-Reesink, Ludger
• Granted Patent: US 6,542,003 B2
• Time in Patent Office: Days
• US Class Current: 375/257
• CPC Class Codes: H04L 25/0268 with modulation and subsequent demodulation

Abstract

In order to enable a simple and cost-effective directly electrically isolated transmission of data signals, the data signals are superposed on a clock signal in an input stage and are transmitted to an output stage in a directly electrically isolated manner via a decoupling device. The clock signal on which the transmitted signals are superposed is filtered out in the output stage. Pulse shape alterations occurring in the signals because of the transmission or because of the filtering-out of the clock signal are compensated in the output stage so that filtered data signals are present at the output of the circuit configuration.

Claims

1. A circuit configuration for performing directly electrically isolated broadband transmission, comprising:

an input stage including at least one logic signal combination device, a first line for transmitting a clock signal, a second line for transmitting a data signal, and a connection to a first ground potential;

an output stage including at least one second logic signal combination device, a filter connected downstream of said second logic signal combination device, and a connection to a second ground potential; and

a decoupling device;

said first logic signal combination device having a first signal input receiving the data signal, and a second signal input receiving the clock signal;

said first logic signal combination device including a first signal output outputting a first output signal to said decoupling device, the first output signal consisting of the data signal superposed on the clock signal;

said decoupling device decoupling said input stage from said output stage by generating a decoupled clock signal from the clock signal and by generating a decoupled first output signal from the first output signal;

said second logic signal combination device including a third signal input receiving the decoupled first output signal from said decoupling device;

said second logic signal combination device including a fourth signal input receiving the decoupled clock signal from said decoupling device;

said second logic signal combination device including a second signal output outputting a second output signal consisting of a decoupled data signal that is separated from the decoupled clock signal;

said second signal output always outputting defined signals;

said filter configured for filtering out interference pulses contained in the second output signal to generate a third output signal that is a filtered decoupled data signal; and

said decoupling device decoupling said input stage from said output stage such that the first ground potential is directly electrically isolated from the second ground potential and such that the clock signal and the first output signal are transmitted in a directly electrically isolated manner from said input stage to said output stage.

2. The circuit configuration according to claim 1, wherein:

said output stage includes at least one third logic signal combination device connected downstream from said filter;

said third logic signal combination device has a fifth signal input receiving the third output signal and a sixth signal input receiving the second ground potential;

said third logic signal combination device is configured such that pulses of the third output signal are converted back into a rectangular form for generating a recovered data signal; and

said third logic signal combination device has a third signal output that outputs the recovered data signal.

3. The circuit configuration according to claim 2, wherein said third logic signal combination device is an XOR gate.

4. The circuit configuration according to claim 2, wherein said third logic signal combination device is an XNOR gate.

5. The circuit configuration according to claim 1, wherein:

said first logic signal combination device is an XOR gate; and

said second logic signal combination device is an XOR gate.

6. The circuit configuration according to claim 5, wherein said third logic signal combination device is an XOR gate.

7. The circuit configuration according to claim 1, wherein:

said first logic signal combination device is an XNOR gate; and

said second logic signal combination device is an XNOR gate.

8. The circuit configuration according to claim 7, wherein said third logic signal combination device is an XNOR gate.

9. The circuit configuration according to claim 1, wherein said decoupling device includes:

at least one first inductive transformer having a primary winding connected to the first ground potential and a secondary winding connected to the second ground potential,

said primary winding connected downstream from said first signal output and said secondary winding connected upstream from third signal input; and

at least one second inductive transformer having a primary winding connected to said first line and the first ground potential and a secondary winding connected to said fourth signal input and the second ground potential.

10. The circuit configuration according to claim 1, wherein said decoupling device includes:

at least one first capacitor connected between said first signal output and said third signal input;

a second capacitor connected between said first line and said second signal input; and

a third capacitor connected between the first ground potential and the second ground potential.

11. The circuit configuration according to claim 1, comprising:

at least one first resistor connected between said second signal input and the second ground potential; and

at least one second resistor connected between said third signal input and the second ground potential.

12. The circuit configuration according to claim 1, wherein said filter includes:

at least one third resistor connected downstream from said second signal output; and

at least one fourth capacitor connected between said third resistor and the second ground potential;

said fourth capacitor having a terminal at which the third output signal is present.

13. The circuit configuration according to claim 1, wherein:

said input stage includes a generator for generating the clock signal; and

said generator is connected between the first ground potential and said first line.

15. The method according to claim 14, which comprises converting pulses of the third output signal back into a rectangular form to convert the third output signal into a recovered data signal.

16. The method according to claim 15, which comprises:

inductively performing the step of transmitting the first output signal and the clock signal; and

inductively performing the step of directly electrically isolating the first ground potential from the second ground potential.

17. The method according to claim 15, which comprises:

using an electric field to perform the step of transmitting the first output signal and the clock signal; and

using a capacitor to perform the step of directly electrically isolating the first ground potential from the second ground potential.

18. The method according to claim 14, which comprises:

inductively performing the step of transmitting the first output signal and the clock signal; and

inductively performing the step of directly electrically isolating the first ground potential from the second ground potential.

19. The method according to claim 14, which comprises:

using an electric field to perform the step of transmitting the first output signal and the clock signal; and

using a capacitor to perform the step of directly electrically isolating the first ground potential from the second ground potential.

14. A method for performing directly electrically isolated broadband transmission, which comprises:

in an input stage, superimposing a data signal on a clock signal to obtain a first output signal by logically combining the data signal and the clock signal;

transmitting the first output signal and the clock signal in a directly electrically isolated manner to an output stage;

directly electrically isolating a first ground potential of the input stage from a second ground potential of the output stage;

in the output stage, logically combining the first output signal that has been transmitted and the clock signal that has been transmitted to thereby form a second output signal that is a decoupled data signal which is transmitted in a directly electrically isolated manner and which is separated from a decoupled clock signal; and

filtering the second output signal to remove interference pulses contained in the second output signal and to thereby generate a filtered data signal defining a third output signal.