Digital phase locked loop for regenerating the clock of an embedded signal

• US 20020122515A1
• Filed: 07/26/2001
• Published: 09/05/2002
• Est. Priority Date: 01/24/2001
• Status: Active Grant

• Current Assignee: Avago Technologies International Sales Pte Limited (Broadcom, Inc.)
• Original Assignee: Broadcom Corporation (Broadcom, Inc.)
• Inventors: Bodenschatz, John
• Granted Patent: US 7,161,998 B2
• Time in Patent Office: Days
• US Class Current: 375/354
• CPC Class Codes: H03L 2207/50 All digital phase-locked loop
• CPC Class Codes: H03L 7/085 concerning mainly the frequency- or phase-detection arrangement including the filtering or amplification of its output signal H03L7/10 takes precedence; circuits for comparing the phase or frequency of two mutually-independent oscillations H03D13/00
• CPC Class Codes: H03L 7/0991 the oscillator being a digital oscillator, e.g. composed of a fixed oscillator followed by a variable frequency divider H03L7/0995 takes precedence; fixed oscillators with means for selecting among various phases H03L7/0814
• CPC Class Codes: H04J 3/062 Synchronisation of signals having the same nominal but fluctuating bit rates, e.g. using buffers pulse-stuffing H04J3/07; asynchronous-synchronous conversion H04L5/24; speed conversion H04L25/05; speed conversion in computers G06F5/06
• CPC Class Codes: H04N 21/4305 Synchronising client clock from received content stream, e.g. locking decoder clock with encoder clock, extraction of the PCR packets arrangements for synchronising receiver with transmitter by comparing receiver clock with transmitter clock H04L7/0012; arrangements for synchronising receiver with transmitter wherein the receiver takes measures against momentary loss of synchronisation H04L7/0083
• CPC Class Codes: H04N 5/06 Generation of synchronising signals
• CPC Class Codes: H04N 5/126 whereby the synchronisation signal indirectly commands a frequency generator
• CPC Class Codes: H04N 7/56 Synchronising systems therefor

Abstract

The present invention relates to a system and method for generating a first clock frequency for a plurality of digital data bursts compressed in time, where each of the plurality of digital data bursts has been multiplexed into one of a plurality of data blocks of higher speed digital data. The system and method includes acquiring the width in data elements of a digital data burst and the width in data elements of a data block of higher speed digital data. The width of one period of a clock pulse is computed at the first clock frequency. A clock pulse is generated at the first clock frequency.

Claims

1. A system for generating a first clock frequency for a plurality of data bursts compressed in time, the system comprising:

a transmitter for transmitting a composite stream using the data bursts clocked at a second clock frequency; and

a receiver for acquiring said composite stream and generating the first clock frequency.

2. The system of claim 1, wherein said second clock frequency is higher than the first clock frequency.

3. The system of claim 1, wherein said receiver includes a de-multiplexer for outputting the data bursts at the first clock frequency.

4. The system of claim 3, wherein said de-multiplexer includes a FIFO circuit.

5. The system of claim 3, wherein said de-multiplexer includes a phase locked loop adapted to generate the first clock frequency using said second clock frequency.

6. The system of claim 5, wherein said digital phase locked loop includes a second order feedback loop.

7. The system of claim 6, wherein said second order feedback loop includes a half period calculator circuit.

8. A system for generating a first clock frequency for a plurality of digital data sub-blocks compressed in time, said system comprising:

a multiplexer for multiplexing each of the plurality of digital data sub-blocks into a plurality of data blocks of higher speed digital data;

a receiver for acquiring the width in data elements of a digital data sub-block and the width in data elements of a data block of higher speed digital data; and

a phase locked loop for computing the width of one period of a clock pulse at the first clock frequency, and generating a clock pulse at the original clock frequency.

9. A system for generating digital data bursts at a first clock rate, the system comprising:

means for acquiring a composite stream;

means for determining the audio pixels per line in said acquired composite stream; and

means for determining the first clock rate.

10. The system of claim 9, further including a means for forming said composite stream.

11. The system of claim 10, wherein said forming means includes a transmitter.

13. The method of claim 12, including transmitting said composite stream at a second clock rate.

14. The method of claim 13, wherein said second clock rate is greater than the first clock rate.

15. The method of claim 12, including computing the average number of audio pixels per line.

16. The method of claim 12, wherein determining the first clock includes using a total line width and number of audio pixels in each line.

17. The method of claim 12, including inserting audio data into video data forming said composite stream.

18. The method of claim 12, including acquiring a width in data elements of a digital data burst.

19. The method of claim 12, including acquiring a width in data elements of a data block of higher speed digital data.

20. The method of claim 12, including computing a width of one period of a clock pulse at the first clock frequency.

12. A method of generating data bursts at a first clock rate, said method comprising the steps of:

forming a composite stream of audio and video data;

acquiring said composite stream; and

determining the first clock rate for the data bursts from said composite stream.

21. A method of generating a first clock frequency for a plurality of digital data bursts, compressed in time, where each of the plurality of digital data bursts has been multiplexed into one of a plurality of data blocks of higher speed digital data, said method comprising the steps of:

acquiring the width in data elements of a digital data burst;

acquiring the width in data elements of a data block of higher speed digital data;

computing the width of one period of a clock pulse at the first clock frequency; and

generating a clock pulse at the first clock frequency.

22. A method of generating a first clock frequency for a plurality of digital data sub-blocks compressed in time, where each of the plurality of digital data sub-blocks has been multiplexed into one of a plurality of data blocks of higher speed digital data, comprising the steps of:

acquiring the width in data elements of a digital data sub-block;

acquiring the width in data elements of a data block of higher speed digital data;

computing the width of one period of a clock pulse at the first clock frequency; and

generating a clock pulse at the first clock frequency.

23. A method of generating a first clock frequency for a burst of digital data compressed in time, wherein the burst of digital data has been multiplexed into a block of higher speed digital data, comprising the steps of:

acquiring the width in data elements of the burst of digital data;

acquiring the width in data elements of the block of higher speed digital data;

computing the width of one period of a clock pulse at the first clock frequency; and

generating a clock pulse at the first clock frequency.

24. A method of generating a first clock frequency for a sub-block of digital data compressed in time, which has been multiplexed into a block of higher speed digital data, comprising the steps of:

acquiring the width in data elements of the sub-block of digital data;

acquiring the width in data elements of the block of higher speed digital data;

computing the width of one period of a clock pulse at the first clock frequency; and

generating a clock pulse at the first clock frequency.