Data processing system having redirecting circuitry and method therefor

• US 20020124161A1
• Filed: 03/05/2001
• Published: 09/05/2002
• Est. Priority Date: 03/05/2001
• Status: Active Grant

• Current Assignee: MOSAID Technologies Inc. (f/k/a Conversant Intellectual Property Management)
• Original Assignee: Freescale Semiconductor, Inc. (NXP Semiconductors NV)
• Inventors: Scott, Jeffrey W., Moyer, William C., Arends, John H.
• Granted Patent: US 6,865,667 B2
• Time in Patent Office: Days
• US Class Current: 712/234
• CPC Class Codes: G06F 8/66 of program code stored in read-only memory [ROM]
• CPC Class Codes: G06F 9/3017 Runtime instruction translation, e.g. macros
• CPC Class Codes: G06F 9/30185 according to one or more bits in the instruction, e.g. prefix, sub-opcode
• CPC Class Codes: G06F 9/328 for runtime instruction patching

Abstract

Embodiments of the present invention relate generally to data processing systems having redirecting circuitry. For example, one embodiment relates to redirecting program flow in a data processing system having a data processor for executing instructions, and circuitry that redirects program flow by identifying an address corresponding to an instruction provided to the data processor for which program execution should be redirected when the instruction is decoded by the data processor. The circuitry also generates a control field having an offset corresponding to the address and using the control field to determine when program flow should be redirected. The circuitry creates a redirected address value by combining a portion of the control field with a predetermined address. The data processor implements redirection of program flow by utilizing the redirected address value. Embodiments also relate to redirecting data accesses and to redirecting program flow while remaining in a same execution context.

Claims

1. A data processing system comprising:

a data processor for executing instructions; and

a memory coupled to the data processor, the memory providing instructions to the data processor for execution;

the data processing system further comprising;

circuitry that redirects program flow by identifying an address corresponding to an instruction provided to the data processor for which program execution should be redirected when the instruction is decoded by the data processor, the circuitry for redirecting program flow also generating a control field having an offset specifically corresponding to the address and using the control field to determine when program flow should be redirected, the circuitry for redirecting program flow creating a redirected address value by combining a portion of the control field to a predetermined address, the data processor receiving the instruction, but discarding the instruction prior to execution completion, the data processor implementing redirection of program flow by utilizing the redirected address value.

2. The data processing system of claim 1 further comprising:

a first storage device wherein the redirected address value is used to form a pointer into the first storage device, the first storage device containing a plurality of code pointers; and

a second storage device, the second storage device containing code for execution by the data processor in lieu of the instruction that was received but discarded.

3. The data processing system of claim 2 wherein the code in the second storage device is executed by the data processor without providing the data processor a substitute operational code (opcode) value in order to redirect execution.

4. The data processing system of claim 1 wherein the circuitry that redirects program flow is redirecting program flow to implement memory patching of the memory wherein user identified instructions which the memory provides to the data processor are substituted with alternate instructions.

5. The data processing system of claim 1 wherein the circuitry that redirects program flow further comprises:

compare circuitry for receiving addresses corresponding to memory locations in the memory and comparing the addresses to one or more predetermined addresses, the compare circuitry providing a match output signal in response to detecting a match;

an encoder coupled to the compare circuitry, the encoder translating a match output signal to a predetermined offset value and generating the control field in response thereto; and

a register coupled to the encoder for receiving and storing the control field.

6. The data processing system of claim 5 wherein the register is an extension of an instruction register which stores the instruction within the data processor.

7. The data processing system of claim 5 further comprising:

an address bus coupled to the encoder for coupling a predetermined portion of address bits of the addresses corresponding to memory locations in the memory for use in generating the control field, the use of the predetermined portion of address bits creating additional control field values.

8. The data processing system of claim 5 wherein the compare circuitry further comprises:

an address mask that reduces a number of address bits that are used to detect the match, the address mask expanding a total number of address values that trigger redirecting program flow.

9. The data processing system of claim 1 further comprising:

a base register for storing the predetermined address, the predetermined address being variable by a user of the data processing system and permitting additional flexibility regarding where redirection of program flow is made.

10. The data processing system of claim 1 wherein the data processing system is in either a user mode context or a supervisor context and no change in context occurs upon redirecting program flow.

11. A method of redirecting program flow in a data processing system comprising:

providing instructions to a data processor for decoding and execution;

identifying an address corresponding to an instruction provided to the data processor for which program execution is to be redirected;

generating a control field having an offset specifically corresponding to the address; and

using the control field to determine when program flow should be redirected and creating a redirected address value by combining a portion of the control field and a predetermined address, wherein the instruction is discarded prior to execution completion and the data processor implements redirection of program flow by using the redirected address value and without providing the data processor with substitute code in order to redirect execution.

12. The method of claim 11 wherein the step of generating a control field further comprises:

generating at least one bit which indicates that program redirection should occur; and

generating one or more bits as the portion of the control field that is combined with the predetermined address, the one or more bits representing an offset value and the predetermined address representing a base address.

13. The method of claim 11, wherein the step of generating a control field further comprises:

generating an offset value to combine with the predetermined address if program redirection should occur; and

generating a predetermined default value if program redirection should not occur.

14. The method of claim 11 further comprising:

using the redirected address value as a ROM patch address to address a patch pointer table, the patch pointer table containing a plurality of patch code pointers; and

selecting one of the plurality of patch code pointers and using the one of the plurality of patch code pointers to address a patch code memory, the patch code memory containing code which is substituted for the instruction.

15. The method of claim 11 wherein the identifying the address corresponding to the instruction provided to the data processor further comprises recognizing whether the address has an address value within a range of addresses or recognizing when a predetermined number of bits of the address have one or more predetermined values to generate the control field.

16. The method of claim 11 further comprising:

using a storage device to store the predetermined address, the storage device allowing a user of the data processing system to vary where program flow redirection occurs.

17. The method of claim 11 further comprising:

storing the control field in an instruction register.

19. The data processing system of claim 18 further comprising means for permitting a user to vary a target memory location where the redirected memory patch address value ultimately points program execution to.

20. The data processing system of claim 18 wherein the redirected memory patch address value is an address in a memory patch pointer table containing memory patch code pointers, each of the memory patch code pointers pointing to code in a patch code memory which is used in lieu of the instruction.

21. The data processing system of claim 18 wherein the data processing system is in either a user mode context or a supervisor context and implementing the memory patch does not change the context of the data processing system.

18. A data processing system with memory patching comprising:

a data processor for executing instructions;

embedded memory contained within a same integrated circuit as the data processor and coupled to the data processor containing instructions which need to have execution avoided if addressed;

external memory coupled to the data processor and embedded memory, the external memory being external to the same integrated circuit; and

circuitry within the same integrated circuit that implements a memory patch by identifying an address corresponding to an instruction provided to the data processor for which a memory patch is required, the circuitry for implementing the memory patch also generating a control field having an offset specifically assigned to the address and using the control field to signal that a memory patch should occur, the circuitry for implementing the memory patch creating a redirected memory patch address value by combining a portion of the control field to a predetermined base address, the data processor receiving the instruction, but discarding the instruction prior to execution completion, the data processor implementing the memory patch by utilizing the redirected memory patch address value.

22. A data processing system comprising:

a data processor for executing instructions that load data from memory; and

a memory coupled to the data processor, the memory providing data to the data processor in response to the instructions;

the data processing system further comprising;

circuitry that redirects a data access by identifying an address corresponding to a data access requested by an instruction for which a substitute data value should be provided, the circuitry for redirecting also generating a control field having an offset specifically corresponding to the address and using the control field to determine when the data access should be redirected, the circuitry for redirecting creating a redirected address value by combining a portion of the control field to a predetermined address, the data processor implementing redirection of a data access by utilizing the redirected address value to access the substitute data value.

23. The data processing system of claim 22 further comprising:

a first storage device wherein the redirected address value is used to form a pointer into the first storage device, the first storage device containing a plurality of code pointers; and

a second storage device, the second storage device containing the substitute data which is referenced by one of the plurality of code pointers.

24. The data processing system of claim 22 further comprising:

a first storage device wherein the redirected address value is used to form a pointer into the first storage device, the first storage device containing a plurality of code pointers; and

a second storage device, the second storage device containing an instruction to access the substitute data which is referenced by one of the plurality of code pointers.

25. The data processing system of claim 24 wherein the instruction in the second storage device is executed by the data processor without providing the data processor a substitute operational code (opcode) value in order to redirect execution.

26. The data processing system of claim 22 further comprising:

a first storage device wherein the redirected address value is used to form a pointer into the first storage device, the first storage device containing the substitute value.

27. The data processing system of claim 22 wherein the circuitry that redirects a data access is redirecting to implement memory patching of the memory wherein accessed data which the memory provides to the data processor are substituted with alternate data values.

28. The data processing system of claim 22 wherein the circuitry that redirects a data access further comprises:

compare circuitry for receiving addresses corresponding to memory locations in the memory and comparing the addresses to one or more predetermined addresses, the compare circuitry providing a match output signal in response to detecting a match;

an encoder coupled to the compare circuitry, the encoder translating a match output signal to a predetermined offset value and generating the control field in response thereto; and

a register coupled to the encoder for receiving and storing the control field.

29. The data processing system of claim 28 wherein the register is an extension of a data register which stores data received in response to data accesses.

30. The data processing system of claim 28 further comprising:

an address bus coupled to the encoder for coupling a predetermined portion of address bits of the addresses corresponding to memory locations in the memory for use in generating the control field, the use of the predetermined portion of address bits creating additional control field values.

31. The data processing system of claim 22 wherein the data processing system is in either a user mode context or a supervisor context and no change in context occurs upon redirecting program flow.

32. A method of redirecting data accesses in a data processing system comprising:

providing instructions to a data processor for execution;

identifying an address corresponding to a data access provided to the data processor in response to an instruction for loading data from memory and for which a substitute data value is to be provided;

generating a control field having an offset specifically corresponding to the address; and

using the control field to determine when data accesses should be redirected and creating a redirected address value by combining a portion of the control field and a predetermined address, wherein the data processor implements redirection by using the redirected address value to access the substitute data value.

33. The method of claim 32 wherein the step of generating a control field further comprises:

generating at least one bit which indicates that redirection should occur; and

generating one or more bits as the portion of the control field that is combined with the predetermined address, the one or more bits representing an offset value and the predetermined address representing a base address.

34. The method of claim 32, wherein the step of generating a control field further comprises:

generating an offset value to combine with the predetermined address if redirection should occur; and

generating a predetermined default value if redirection should not occur.

35. The method of claim 32 further comprising:

using the redirected address value as a ROM patch address to address a patch pointer table, the patch pointer table containing a plurality of patch code pointers; and

selecting one of the plurality of patch code pointers and using the one of the plurality of patch code pointers to address a patch code memory, the patch code memory containing the substitute data value.

36. The method of claim 32 further comprising:

using the redirected address value as a ROM patch address to address a patch pointer table, the patch pointer table containing a plurality of patch code pointers; and

selecting one of the plurality of patch code pointers and using the one of the plurality of patch code pointers to address a patch code memory, the patch code memory containing the instructions to access the substitute data value.

37. The method of claim 32 further comprising:

using the redirected address value as a ROM patch address to address a patch pointer table, the patch pointer table containing the substitute data value.

38. The method of claim 32 further comprising:

storing the control field in a data register.