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Testing apparatus and testing method for an integrated circuit, and integrated circuit

  • US 20020124217A1
  • Filed: 12/04/2001
  • Published: 09/05/2002
  • Est. Priority Date: 12/07/2000
  • Status: Active Grant
First Claim
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1. A testing apparatus for an integrated circuit comprising:

  • a pattern generator built in said integrated circuit to generate test patterns;

    a plurality of shift registers configured with sequential circuit elements inside said integrated circuit; and

    a pattern modifier for modifying said test patterns generated by said pattern generator according to an external input, and inputting said modified test patterns to said shift registers.

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