Method and apparatus for pre-computing and using placement costs within a partitioned region for multiple wiring models
First Claim
1. For an electronic design automation application, a partitioning method of placing circuit modules in a region of an integrated circuit (“
- IC”
) layout, wherein said IC layout includes nets and a plurality of circuit elements, each net representing interconnections between a set of circuit elements in the IC layout, the method comprising;
a) defining a plurality of partitioning lines that divide the IC region into several sub-regions;
b) identifying the set of sub-regions containing the circuit elements of a net, said set of sub-regions representing the net'"'"'s configuration with respect to the defined partitioning lines;
wherein a connection graph models the net'"'"'s configuration with respect to the defined partitioning lines;
said connection graph having an edge that is completely or partially diagonal; and
c) identifying an attribute of the connection graph.
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Accused Products
Abstract
One embodiment of the invention is a recursive partitioning method that places circuit elements in an IC layout. This method initially defines a number of partitioning lines that divide an IC region into several sub-regions (also called slots). For a net in the region, the method then identifies the set of sub-regions (i.e., the set of slots) that contain the circuit elements (e.g., the pins of circuit modules) of that net. The set of sub-regions for the net represents the net'"'"'s configuration with respect to the defined partitioning lines. Next, the placement method identifies attribute or attributes of a connection graph that models the net'"'"'s configuration with respect to the partitioning lines. The connection graph for each net provides a topology of interconnect lines that connect the slots that contain the net'"'"'s circuit elements. According to some embodiments of the invention, the connection graph for each net can have edges that are completely or partially diagonal.
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Citations
27 Claims
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1. For an electronic design automation application, a partitioning method of placing circuit modules in a region of an integrated circuit (“
- IC”
) layout, wherein said IC layout includes nets and a plurality of circuit elements, each net representing interconnections between a set of circuit elements in the IC layout, the method comprising;
a) defining a plurality of partitioning lines that divide the IC region into several sub-regions;
b) identifying the set of sub-regions containing the circuit elements of a net, said set of sub-regions representing the net'"'"'s configuration with respect to the defined partitioning lines;
wherein a connection graph models the net'"'"'s configuration with respect to the defined partitioning lines;
said connection graph having an edge that is completely or partially diagonal; and
c) identifying an attribute of the connection graph. - View Dependent Claims (2, 3, 4, 5, 6, 7, 8, 9, 10, 11, 12, 13, 14, 15, 16, 17, 18, 20, 21, 22, 23, 24, 25, 26, 27)
- IC”
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19. For an electronic design automation (“
- EDA”
) application that performs a placement process, a method of pre-computing costs of placements of circuit modules in regions of integrated circuit (“
IC”
) layouts, the method comprising;
a) defining a partitioning grid with N number of slots, said partitioning grid for partitioning a region of an IC layout into N sub-regions during the placement process of the EDA application;
b) for each particular grouping of slots of said grid, constructing a connection graph that models the topology of interconnect lines needed to connect said particular group of slots;
c) computing an attribute of each of the constructed connection graphs;
d) storing said attribute in a data structure.
- EDA”
Specification