Semiconductor device and method of producing the same

• US 20020125575A1
• Filed: 01/10/2002
• Published: 09/12/2002
• Est. Priority Date: 12/10/1998
• Status: Abandoned Application

• Current Assignee: Katsuhiro Chaen
• Original Assignee: Katsuhiro Chaen
• Inventors: Chaen, Katsuhiro
• Application Number:
  US10/044,245
• Publication Number:
  US 20020125575A1
• Time in Patent Office: Days
• US Class Current: 257/758
• CPC Class Codes: H01F 17/0006 Printed inductances printed coils for dynamo-electric machines H02K3/26; printed circuits H05K
• CPC Class Codes: H01F 2027/2861 Coil formed by folding a blank
• CPC Class Codes: H01L 2224/05001 Internal layers
• CPC Class Codes: H01L 2224/05005 Structure
• CPC Class Codes: H01L 2224/05022 the internal layer being at least partially embedded in the surface
• CPC Class Codes: H01L 2224/05144 Gold [Au] as principal constituent
• CPC Class Codes: H01L 2224/05166 Titanium [Ti] as principal constituent
• CPC Class Codes: H01L 2224/05541 Structure
• CPC Class Codes: H01L 2224/05572 the external layer extending out of an opening
• CPC Class Codes: H01L 2224/05644 Gold [Au] as principal constituent
• CPC Class Codes: H01L 23/5227 Inductive arrangements or effects of, or between, wiring layers other inductive arrangements H01L23/645
• CPC Class Codes: H01L 24/03 Manufacturing methods
• CPC Class Codes: H01L 24/05 of an individual bonding area
• CPC Class Codes: H01L 24/11 Manufacturing methods for bumps on insulating substrates H01L21/4853
• CPC Class Codes: H01L 2924/00 Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
• CPC Class Codes: H01L 2924/00014 the subject-matter covered by the group, the symbol of which is combined with the symbol of this group, being disclosed without further technical details
• CPC Class Codes: H01L 2924/14 Integrated circuits
• CPC Class Codes: H01L 2924/3011 Impedance

Abstract

To prevent collapse and delamination without increasing an occupied area or to reduce the area while maintaining a necessary strength, an inductor is provided by being formed on a first insulating layer on a semiconductor substrate comprises a plurality of metal layers stacked on the first insulating layer. Among the plurality of metal layers, the second insulating layer extends over the end portion of the lower-most metal layer from the first insulating layer. The other metal layers comprising the inductor are formed in contact with the upper surface of the lower-most metal layer which is not covered with the second insulating layer. The lower-most metal layer is preferably formed on the first insulating layer via a bonding layer (not shown). The lower-most layer is pressed down at the circumference by the second insulating layer, so an external force is not imposed directly on the interface between the metal layer and the insulating layer.

Claims

1. A semiconductor device having an inductor, comprising:

a substrate;

a first metal layer formed on the substrate;

an insulating layer formed on the first metal layer;

an opening formed in the insulating layer; and

a second metal layer formed on the opening;

said insulating layer covering an end portion of said first metal layer.

2. A semiconductor device as set forth in claim 1, further comprising a second insulating layer between said substrate and said first metal layer.

3. A semiconductor device as set forth in claim 2, further comprising a bonding layer having a higher bonding strength to the second insulating layer than the first metal layer does between said second insulating layer and said first metal layer.

4. A semiconductor device as set forth in claim 3, wherein said bonding layer is Ti.

5. A semiconductor device as set forth in claim 1, wherein said inductor is formed in a spiral shape.

6. A semiconductor device having an inductance comprising:

a substrate;

a first metal layer on the substrate formed to be a pattern for configuring the above inductance;

a first insulation layer having an opening positioned on the upper portion of the first metal film, covering the circumference of said first metal layer, and continuously extending on said substrate from the circumference; and

a second metal layer connected with said first metal layer via the opening of said first insulation layer, positioned above said first metal layer and configuring said inductance together with said first metal layer.

7. A semiconductor device having an inductance as set forth in claim 6, wherein said second metal film comprising:

a third metal layer having a thickness of about the same as that of said first insulation layer; and

a fourth metal layer formed above the third metal layer having a thicker thickness than those of the first metal layer and the third metal layer.

8. A semiconductor device having an inductance as set forth in claim 7, wherein:

said third metal film fills the openings formed on said first insulation layer; and

said forth metal film is a size of said opening and extends there above.

9. A semiconductor device having an inductance as set forth in claim 7, wherein:

said first and third metal films are formed by vapor deposition or sputtering; and

said fourth metal film is formed by plating method.

10. A semiconductor device having an inductance as set forth in claim 6;

wherein said second metal film comprises a fourth metal film formed on said first metal film and has a thicker thickness than that of the first metal film.

11. A semiconductor device having an inductance as set forth in claim 10, wherein:

said fourth metal film is formed to fill the opening of said first insulation layer to connect to said first metal film and extend over the portion covering the circumference of said first metal film of said first insulation layer.

12. A semiconductor device having an inductance as set forth in claim 11, wherein

said first metal film is formed by vapor deposition or sputtering;

and

said fourth metal film is formed by plating method.

13. A semiconductor device as set forth in claim 6, wherein said bonding layer is Ti.

14. A semiconductor device as set forth in claim 6, wherein:

said substrate is a GaAs substrate; and

said plurality of metal layers comprising the inductor is Au.

15. A semiconductor device having an inductor as set forth in claim 6, wherein

said substrate is a semiconductor substrate;

a second insulation layer is formed between said substrate and said first metal film; and

said first insulation layer has an opening positioned above said first metal film, covers a circumference of said first metal film and continuously extends over said second insulation layer from the circumference.

16. A semiconductor device having an inductance as set forth in claim 15, wherein said substrate is a GaAs substrate.

17. A semiconductor device having an inductance as set forth in claim 16, wherein said first and second insulating layers are formed by silicon nitride.

18. A semiconductor device having an inductor as set forth in claim 6, wherein said substrate is a semi-insulating semiconductor substrate.

19. A semiconductor device having an inductance as set forth in claim 18, wherein a first insulation layer is formed by silicon nitride.

20. A semiconductor device having an inductance as set forth in claim 6, wherein said first metal film and second metal film are formed in a spiral shape on the surface of the substrate to compose the inductance.